Lines Matching refs:ISD
83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
95 setOperationAction(ISD::SRA, MVT::i8, Custom);
96 setOperationAction(ISD::SHL, MVT::i8, Custom);
97 setOperationAction(ISD::SRL, MVT::i8, Custom);
98 setOperationAction(ISD::SRA, MVT::i16, Custom);
99 setOperationAction(ISD::SHL, MVT::i16, Custom);
100 setOperationAction(ISD::SRL, MVT::i16, Custom);
101 setOperationAction(ISD::ROTL, MVT::i8, Expand);
102 setOperationAction(ISD::ROTR, MVT::i8, Expand);
103 setOperationAction(ISD::ROTL, MVT::i16, Expand);
104 setOperationAction(ISD::ROTR, MVT::i16, Expand);
105 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
106 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
107 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
108 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
109 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
110 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
111 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
112 setOperationAction(ISD::SETCC, MVT::i8, Custom);
113 setOperationAction(ISD::SETCC, MVT::i16, Custom);
114 setOperationAction(ISD::SELECT, MVT::i8, Expand);
115 setOperationAction(ISD::SELECT, MVT::i16, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
118 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
119 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
120 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
122 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
123 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
124 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand);
125 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
126 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
127 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand);
129 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Expand);
130 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
131 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
133 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
134 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
135 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
136 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
137 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
138 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
143 setOperationAction(ISD::MUL, MVT::i8, Expand);
144 setOperationAction(ISD::MULHS, MVT::i8, Expand);
145 setOperationAction(ISD::MULHU, MVT::i8, Expand);
146 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
147 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
148 setOperationAction(ISD::MUL, MVT::i16, Expand);
149 setOperationAction(ISD::MULHS, MVT::i16, Expand);
150 setOperationAction(ISD::MULHU, MVT::i16, Expand);
151 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
152 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
154 setOperationAction(ISD::UDIV, MVT::i8, Expand);
155 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
156 setOperationAction(ISD::UREM, MVT::i8, Expand);
157 setOperationAction(ISD::SDIV, MVT::i8, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
159 setOperationAction(ISD::SREM, MVT::i8, Expand);
160 setOperationAction(ISD::UDIV, MVT::i16, Expand);
161 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
162 setOperationAction(ISD::UREM, MVT::i16, Expand);
163 setOperationAction(ISD::SDIV, MVT::i16, Expand);
164 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
165 setOperationAction(ISD::SREM, MVT::i16, Expand);
183 case ISD::SHL: // FALLTHROUGH
184 case ISD::SRL:
185 case ISD::SRA: return LowerShifts(Op, DAG);
186 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
187 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
188 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
189 case ISD::SETCC: return LowerSETCC(Op, DAG);
190 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
191 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
192 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
193 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
194 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
248 const SmallVectorImpl<ISD::InputArg>
272 const SmallVectorImpl<ISD::OutputArg> &Outs,
274 const SmallVectorImpl<ISD::InputArg> &Ins,
300 const SmallVectorImpl<ISD::InputArg>
342 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
345 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
349 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
381 const SmallVectorImpl<ISD::OutputArg> &Outs,
439 const SmallVectorImpl<ISD::OutputArg>
442 const SmallVectorImpl<ISD::InputArg> &Ins,
473 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
476 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
479 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
493 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
506 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
564 const SmallVectorImpl<ISD::InputArg> &Ins,
597 case ISD::SHL:
600 case ISD::SRA:
603 case ISD::SRL:
615 if (Opc == ISD::SRL && ShiftAmount) {
623 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
660 ISD::CondCode CC,
669 case ISD::SETEQ:
673 if (LHS.getOpcode() == ISD::Constant)
676 case ISD::SETNE:
680 if (LHS.getOpcode() == ISD::Constant)
683 case ISD::SETULE:
685 case ISD::SETUGE:
696 case ISD::SETUGT:
698 case ISD::SETULT:
709 case ISD::SETLE:
711 case ISD::SETGE:
722 case ISD::SETGT:
724 case ISD::SETLT:
744 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
770 (LHS.getOpcode() == ISD::AND ||
771 (LHS.getOpcode() == ISD::TRUNCATE &&
772 LHS.getOperand(0).getOpcode() == ISD::AND))) {
776 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
820 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
821 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
823 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
843 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
867 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
868 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
902 DAG.getNode(ISD::ADD, dl, getPointerTy(),
936 ISD::MemIndexedMode &AM,
940 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
947 if (Op->getOpcode() != ISD::ADD)
958 AM = ISD::POST_INC;
