Lines Matching refs:MSP430
1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
14 #define DEBUG_TYPE "msp430-lower"
17 #include "MSP430.h"
48 HWMultMode("msp430-hwmult-mode",
67 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
68 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
78 setStackPointerRegisterToSaveRestore(MSP430::SPW);
201 // MSP430 Inline Assembly Support
229 return std::make_pair(0U, MSP430::GR8RegisterClass);
231 return std::make_pair(0U, MSP430::GR16RegisterClass);
277 // MSP430 target does not yet support tail call optimization.
334 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
491 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
816 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
922 MSP430::FPW, VT);
1000 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1005 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1025 case MSP430::Shl8:
1026 Opc = MSP430::SHL8r1;
1027 RC = MSP430::GR8RegisterClass;
1029 case MSP430::Shl16:
1030 Opc = MSP430::SHL16r1;
1031 RC = MSP430::GR16RegisterClass;
1033 case MSP430::Sra8:
1034 Opc = MSP430::SAR8r1;
1035 RC = MSP430::GR8RegisterClass;
1037 case MSP430::Sra16:
1038 Opc = MSP430::SAR16r1;
1039 RC = MSP430::GR16RegisterClass;
1041 case MSP430::Srl8:
1042 Opc = MSP430::SAR8r1c;
1043 RC = MSP430::GR8RegisterClass;
1045 case MSP430::Srl16:
1046 Opc = MSP430::SAR16r1c;
1047 RC = MSP430::GR16RegisterClass;
1075 unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1076 unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1086 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1088 BuildMI(BB, dl, TII.get(MSP430::JCC))
1097 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1100 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1105 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1107 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1113 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1126 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1127 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1128 Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1134 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1167 BuildMI(BB, dl, TII.get(MSP430::JCC))
1183 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
