Lines Matching refs:VReg
766 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
767 MF.getRegInfo().addLiveIn(PReg, VReg);
768 return VReg;
795 // destination vreg to set, the condition code register to branch on, the
2706 unsigned VReg = AddLiveIn(MF, *Reg, Mips::CPU64RegsRegisterClass);
2709 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
