Lines Matching refs:addReg
828 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
829 .addReg(Mips::ZERO).addMBB(sinkMBB);
847 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
848 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
852 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
853 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1038 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1042 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1043 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1046 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1050 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1051 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1130 .addReg(Mips::ZERO).addImm(-4);
1132 .addReg(Ptr).addReg(MaskLSB2);
1133 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1134 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1136 .addReg(Mips::ZERO).addImm(MaskImm);
1138 .addReg(ShiftAmt).addReg(MaskUpper);
1139 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1140 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1162 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1167 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1169 .addReg(Mips::ZERO).addReg(AndRes);
1170 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1174 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1175 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1178 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1182 .addReg(OldVal).addReg(Mask2);
1184 .addReg(MaskedOldVal0).addReg(NewVal);
1186 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1188 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1199 .addReg(OldVal).addReg(Mask);
1201 .addReg(ShiftAmt).addReg(MaskedOldVal1);
1203 .addReg(SrlRes).addImm(ShiftImm);
1205 .addReg(SllRes).addImm(ShiftImm);
1276 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1278 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1285 .addReg(NewVal).addReg(Ptr).addImm(0);
1287 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1373 .addReg(Mips::ZERO).addImm(-4);
1375 .addReg(Ptr).addReg(MaskLSB2);
1376 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1377 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1379 .addReg(Mips::ZERO).addImm(MaskImm);
1381 .addReg(ShiftAmt).addReg(MaskUpper);
1382 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1384 .addReg(CmpVal).addImm(MaskImm);
1386 .addReg(ShiftAmt).addReg(MaskedCmpVal);
1388 .addReg(NewVal).addImm(MaskImm);
1390 .addReg(ShiftAmt).addReg(MaskedNewVal);
1397 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1399 .addReg(OldVal).addReg(Mask);
1401 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1410 .addReg(OldVal).addReg(Mask2);
1412 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1414 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1416 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1426 .addReg(ShiftAmt).addReg(MaskedOldVal0);
1428 .addReg(SrlRes).addImm(ShiftImm);
1430 .addReg(SllRes).addImm(ShiftImm);
