Lines Matching defs:VT
314 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
316 // add/sub are legal for all supported vector VT's.
317 setOperationAction(ISD::ADD , VT, Legal);
318 setOperationAction(ISD::SUB , VT, Legal);
321 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
322 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
325 setOperationAction(ISD::AND , VT, Promote);
326 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
327 setOperationAction(ISD::OR , VT, Promote);
328 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
329 setOperationAction(ISD::XOR , VT, Promote);
330 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
331 setOperationAction(ISD::LOAD , VT, Promote);
332 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
333 setOperationAction(ISD::SELECT, VT, Promote);
334 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
335 setOperationAction(ISD::STORE, VT, Promote);
336 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
339 setOperationAction(ISD::MUL , VT, Expand);
340 setOperationAction(ISD::SDIV, VT, Expand);
341 setOperationAction(ISD::SREM, VT, Expand);
342 setOperationAction(ISD::UDIV, VT, Expand);
343 setOperationAction(ISD::UREM, VT, Expand);
344 setOperationAction(ISD::FDIV, VT, Expand);
345 setOperationAction(ISD::FNEG, VT, Expand);
346 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
347 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
348 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
349 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
350 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
351 setOperationAction(ISD::UDIVREM, VT, Expand);
352 setOperationAction(ISD::SDIVREM, VT, Expand);
353 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
354 setOperationAction(ISD::FPOW, VT, Expand);
355 setOperationAction(ISD::CTPOP, VT, Expand);
356 setOperationAction(ISD::CTLZ, VT, Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
358 setOperationAction(ISD::CTTZ, VT
359 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
511 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
1091 EVT VT;
1094 VT = LD->getMemoryVT();
1098 VT = ST->getMemoryVT();
1103 if (VT.isVector())
1109 if (VT != MVT::i64) {
1267 EVT VT = Op.getOperand(0).getValueType();
1269 if (VT.bitsLT(MVT::i32)) {
1270 VT = MVT::i32;
1271 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1273 unsigned Log2b = Log2_32(VT.getSizeInBits());
1274 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1275 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1293 EVT VT = Op.getValueType();
1296 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1304 EVT VT = Node->getValueType(0);
1319 if (VT == MVT::i64) {
1360 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1365 VT.isInteger() ? GprIndex : FprIndex,
1366 DAG.getConstant(VT.isInteger() ? 4 : 8,
1374 if (VT.isFloatingPoint())
1378 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1380 VT.isInteger() ? GprIndex : FprIndex,
1381 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1385 VT.isInteger() ? VAListPtr : FprPtr,
1394 DAG.getConstant(VT.isInteger() ? 4 : 8,
1405 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1932 EVT ObjectVT = Ins[ArgNo].VT;
1977 EVT ObjectVT = Ins[ArgNo].VT;
1995 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2264 EVT ArgVT = Outs[i].VT;
2424 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2425 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2437 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2455 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2456 SDValue FIN = DAG.getFrameIndex(FI, VT);
2476 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2478 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2486 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
2752 EVT VT = VA.getValVT();
2755 VA.getLocReg(), VT, InFlag).getValue(1);
2936 MVT ArgVT = Outs[i].VT;
3220 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3223 MachinePointerInfo(), VT,
3405 EVT ArgType = Outs[i].VT;
3802 EVT VT = Op.getValueType();
3839 return DAG.getNode((VT.getSizeInBits() < 16 ?
3840 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3844 EVT VT = Op.getValueType();
3845 unsigned BitWidth = VT.getSizeInBits();
3848 VT == Op.getOperand(1).getValueType() &&
3860 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3861 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3862 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3865 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3866 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3867 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3873 EVT VT = Op.getValueType();
3875 unsigned BitWidth = VT.getSizeInBits();
3877 VT == Op.getOperand(1).getValueType() &&
3889 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3890 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3891 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3894 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3895 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3896 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3903 EVT VT = Op.getValueType();
3904 unsigned BitWidth = VT.getSizeInBits();
3906 VT == Op.getOperand(1).getValueType() &&
3917 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3918 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3919 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3922 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3923 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3935 /// SplatSize. Cast the result to VT.
3936 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3940 static const EVT VTys[] = { // canonical VT to use for each size.
3944 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3985 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3994 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4233 EVT VT = OpLHS.getValueType();
4237 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4250 EVT VT = Op.getValueType();
4350 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4615 EVT VT = N->getValueType(0);
4617 if (VT == MVT::i64) {
5360 DAG.getValueType(N->getValueType(0)) // VT
5608 EVT VT) const {
5614 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5618 if (VT == MVT::f32)
5620 else if (VT == MVT::f64)
5630 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
