Lines Matching refs:ISD
41 ISD::ArgFlagsTy &ArgFlags,
46 ISD::ArgFlagsTy &ArgFlags,
51 ISD::ArgFlagsTy &ArgFlags,
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
85 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
103 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
106 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
108 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
109 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
110 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
113 setOperationAction(ISD::SREM, MVT::i32, Expand);
114 setOperationAction(ISD::UREM, MVT::i32, Expand);
115 setOperationAction(ISD::SREM, MVT::i64, Expand);
116 setOperationAction(ISD::UREM, MVT::i64, Expand);
119 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
120 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
121 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
122 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
123 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
124 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
125 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
126 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
129 setOperationAction(ISD::FSIN , MVT::f64, Expand);
130 setOperationAction(ISD::FCOS , MVT::f64, Expand);
131 setOperationAction(ISD::FREM , MVT::f64, Expand);
132 setOperationAction(ISD::FPOW , MVT::f64, Expand);
133 setOperationAction(ISD::FMA , MVT::f64, Expand);
134 setOperationAction(ISD::FSIN , MVT::f32, Expand);
135 setOperationAction(ISD::FCOS , MVT::f32, Expand);
136 setOperationAction(ISD::FREM , MVT::f32, Expand);
137 setOperationAction(ISD::FPOW , MVT::f32, Expand);
138 setOperationAction(ISD::FMA , MVT::f32, Expand);
140 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
144 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
145 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
148 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
149 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
152 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
153 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
154 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
155 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
156 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
157 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
158 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
159 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
160 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
161 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
164 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
165 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
168 setOperationAction(ISD::SELECT, MVT::i32, Expand);
169 setOperationAction(ISD::SELECT, MVT::i64, Expand);
170 setOperationAction(ISD::SELECT, MVT::f32, Expand);
171 setOperationAction(ISD::SELECT, MVT::f64, Expand);
174 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
175 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
178 setOperationAction(ISD::SETCC, MVT::i32, Custom);
181 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
183 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
190 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
192 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
193 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
194 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
195 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
200 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
201 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
202 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
203 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
208 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
209 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
210 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
211 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
212 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
213 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
214 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
215 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
216 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
217 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
220 setOperationAction(ISD::TRAP, MVT::Other, Legal);
223 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
224 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
227 setOperationAction(ISD::VASTART , MVT::Other, Custom);
232 setOperationAction(ISD::VAARG, MVT::i1, Promote);
233 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
234 setOperationAction(ISD::VAARG, MVT::i8, Promote);
235 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
236 setOperationAction(ISD::VAARG, MVT::i16, Promote);
237 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
238 setOperationAction(ISD::VAARG, MVT::i32, Promote);
239 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
240 setOperationAction(ISD::VAARG, MVT::Other, Expand);
243 setOperationAction(ISD::VAARG, MVT::Other, Custom);
244 setOperationAction(ISD::VAARG, MVT::i64, Custom);
247 setOperationAction(ISD::VAARG, MVT::Other, Expand);
250 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
251 setOperationAction(ISD::VAEND , MVT::Other, Expand);
252 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
253 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
254 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
255 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
258 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
261 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
262 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
263 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
264 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
265 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
266 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
267 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
268 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
269 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
270 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
271 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
272 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
276 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
277 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
278 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
279 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
282 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
287 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
290 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
297 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
299 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
300 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
301 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
304 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
305 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
306 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
317 setOperationAction(ISD::ADD , VT, Legal);
318 setOperationAction(ISD::SUB , VT, Legal);
321 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
322 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
325 setOperationAction(ISD::AND , VT, Promote);
326 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
327 setOperationAction(ISD::OR , VT, Promote);
328 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
329 setOperationAction(ISD::XOR , VT, Promote);
330 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
331 setOperationAction(ISD::LOAD , VT, Promote);
332 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
333 setOperationAction(ISD::SELECT, VT, Promote);
334 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
335 setOperationAction(ISD::STORE, VT, Promote);
336 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
339 setOperationAction(ISD::MUL , VT, Expand);
340 setOperationAction(ISD::SDIV, VT, Expand);
341 setOperationAction(ISD::SREM, VT, Expand);
342 setOperationAction(ISD::UDIV, VT, Expand);
343 setOperationAction(ISD::UREM, VT, Expand);
344 setOperationAction(ISD::FDIV, VT, Expand);
345 setOperationAction(ISD::FNEG, VT, Expand);
346 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
347 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
348 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
349 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
350 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
351 setOperationAction(ISD::UDIVREM, VT, Expand);
352 setOperationAction(ISD::SDIVREM, VT, Expand);
353 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
354 setOperationAction(ISD::FPOW, VT, Expand);
355 setOperationAction(ISD::CTPOP, VT, Expand);
356 setOperationAction(ISD::CTLZ, VT, Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
358 setOperationAction(ISD
359 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
364 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
366 setOperationAction(ISD::AND , MVT::v4i32, Legal);
367 setOperationAction(ISD::OR , MVT::v4i32, Legal);
368 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
369 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
370 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
371 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
378 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
379 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
380 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
381 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
383 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
384 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
386 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
387 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
388 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
389 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
393 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
395 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
396 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
412 setTargetDAGCombine(ISD::SINT_TO_FP);
413 setTargetDAGCombine(ISD::STORE);
414 setTargetDAGCombine(ISD::BR_CC);
415 setTargetDAGCombine(ISD::BSWAP);
523 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
720 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
766 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
805 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
823 if (N->getOpcode() != ISD::Constant)
844 if (N.getOpcode() == ISD::ADD) {
853 } else if (N.getOpcode() == ISD::OR) {
893 if (N.getOpcode() == ISD::ADD) {
908 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
909 Disp.getOpcode() == ISD::TargetConstantPool ||
910 Disp.getOpcode() == ISD::TargetJumpTable);
914 } else if (N.getOpcode() == ISD::OR) {
981 if (N.getOpcode() == ISD::ADD) {
1006 if (N.getOpcode() == ISD::ADD) {
1021 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1022 Disp.getOpcode() == ISD::TargetConstantPool ||
1023 Disp.getOpcode() == ISD::TargetJumpTable);
1027 } else if (N.getOpcode() == ISD::OR) {
1085 ISD::MemIndexedMode &AM,
1123 LD->getExtensionType() == ISD::SEXTLOAD &&
1128 AM = ISD::PRE_INC;
1178 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1183 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1259 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1266 if (C->isNullValue() && CC == ISD::SETEQ) {
1271 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1274 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1275 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1277 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1292 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1294 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1314 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1321 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1324 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1325 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1328 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1333 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1337 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1342 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1345 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1361 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1364 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1370 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1375 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1379 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1390 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1393 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1397 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1525 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1534 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1542 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1555 ISD::ArgFlagsTy &ArgFlags,
1563 ISD::ArgFlagsTy &ArgFlags,
1590 ISD::ArgFlagsTy &ArgFlags,
1627 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1640 const SmallVectorImpl<ISD::InputArg>
1658 const SmallVectorImpl<ISD::InputArg>
1841 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1861 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1866 Chain = DAG.getNode(ISD::TokenFactor, dl,
1876 const SmallVectorImpl<ISD::InputArg>
1933 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1980 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2087 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2090 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2093 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2226 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2231 Chain = DAG.getNode(ISD::TokenFactor, dl,
2244 const SmallVectorImpl<ISD::OutputArg>
2263 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2329 const SmallVectorImpl<ISD::InputArg> &Ins,
2343 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2502 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2527 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2552 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2676 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2740 const SmallVectorImpl<ISD::InputArg> &Ins,
2772 const SmallVectorImpl<ISD::InputArg> &Ins,
2809 assert(((Callee.getOpcode() == ISD::Register &&
2811 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2812 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2870 const SmallVectorImpl<ISD::OutputArg> &Outs,
2872 const SmallVectorImpl<ISD::InputArg> &Ins,
2893 const SmallVectorImpl<ISD::OutputArg> &Outs,
2895 const SmallVectorImpl<ISD::InputArg> &Ins,
2937 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3007 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3022 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3055 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3069 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3102 const SmallVectorImpl<ISD::OutputArg> &Outs,
3104 const SmallVectorImpl<ISD::InputArg> &Ins,
3197 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3205 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3210 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3222 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3231 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3259 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3308 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3352 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3368 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3421 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3435 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3471 const SmallVectorImpl<ISD::OutputArg> &Outs,
3482 const SmallVectorImpl<ISD::OutputArg> &Outs,
3608 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3626 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3629 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3642 case ISD::SETULT:
3643 case ISD::SETLT:
3645 case ISD::SETOGE:
3646 case ISD::SETGE:
3648 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3650 case ISD::SETUGT:
3651 case ISD::SETGT:
3653 case ISD::SETOLE:
3654 case ISD::SETLE:
3656 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3658 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3664 case ISD::SETULT:
3665 case ISD::SETLT:
3666 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3668 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3670 case ISD::SETOGE:
3671 case ISD::SETGE:
3672 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3674 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3676 case ISD::SETUGT:
3677 case ISD::SETGT:
3678 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3680 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3682 case ISD::SETOLE:
3683 case ISD::SETLE:
3684 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3686 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3698 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3704 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3723 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3737 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
3740 FP = DAG.getNode(ISD::FP_ROUND, dl,
3775 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3820 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3826 DAG.getNode(ISD::AND, dl, MVT::i32,
3829 DAG.getNode(ISD::SRL, dl, MVT::i32,
3830 DAG.getNode(ISD::AND, dl, MVT::i32,
3831 DAG.getNode(ISD::XOR, dl, MVT::i32,
3837 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3840 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3858 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3862 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3863 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3866 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3887 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3891 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3892 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3895 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3915 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3919 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3920 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3925 Tmp4, Tmp6, ISD::SETLE);
3956 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3958 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
3967 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3977 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3987 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
3988 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
3994 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4027 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
4028 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
4046 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
4047 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4062 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
4063 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4089 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4100 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4111 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4123 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4149 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
4150 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
4156 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
4157 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
4234 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
4235 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
4237 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4255 if (V2.getOpcode() == ISD::UNDEF) {
4342 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4358 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4424 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
4464 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4467 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4472 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4507 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
4508 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
4509 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
4521 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4535 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
4540 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
4559 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4560 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4561 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4562 case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for PPC");
4563 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4564 case ISD::SETCC: return LowerSETCC(Op, DAG);
4565 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
4566 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
4567 case ISD::VASTART:
4570 case ISD::VAARG:
4573 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4574 case ISD::DYNAMIC_STACKALLOC:
4577 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4578 case ISD::FP_TO_UINT:
4579 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4581 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4582 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4585 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4586 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4587 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4590 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4591 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4592 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4593 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4594 case ISD::MUL: return LowerMUL(Op, DAG);
4597 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4598 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4610 case ISD::VAARG: {
4625 case ISD::FP_ROUND_INREG: {
4628 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4631 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4682 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4686 case ISD::FP_TO_SINT:
5275 case ISD::SINT_TO_FP:
5277 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5285 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5294 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5306 case ISD::STORE:
5310 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5315 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5329 N->getOperand(1).getOpcode() == ISD::BSWAP &&
5336 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5349 case ISD::BSWAP:
5351 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5370 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5436 case ISD::BR_CC: {
5441 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5446 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5447 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5455 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5458 return DAG.getNode(ISD::BR, dl, MVT::Other,
5462 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5523 case ISD::INTRINSIC_WO_CHAIN: {
5775 DAG.getNode(ISD::ADD, dl, getPointerTy(),
