Lines Matching defs:CC
1737 static bool IsTailCallConvention(CallingConv::ID CC) {
1738 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1755 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1757 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
7485 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7486 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7487 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8226 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8287 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8303 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8312 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8313 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8323 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8329 bool Invert = (CC == ISD::SETNE) ^
8340 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8359 SDValue CC = Op.getOperand(2);
8377 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8378 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8386 SDValue CC = Op.getOperand(2);
8388 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8552 SDValue CC;
8606 CC = Cond.getOperand(0);
8615 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8653 CC = DAG.getConstant(X86Cond, MVT::i8);
8667 CC = NewSetCC.getOperand(0);
8675 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8684 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8699 SDValue Ops[] = { Op2, Op1, CC, Cond };
8735 SDValue CC;
8780 CC = Cond.getOperand(0);
8789 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8835 CC = DAG.getConstant(X86Cond, MVT::i8);
8847 CC = Cond.getOperand(0).getOperand(0);
8849 Chain, Dest, CC, Cmp);
8850 CC = Cond.getOperand(1).getOperand(0);
8866 CC = DAG.getConstant(CCode, MVT::i8);
8880 Chain, Dest, CC, Cmp);
8884 CC = DAG.getConstant(CCode, MVT::i8);
8897 CC = DAG.getConstant(CCode, MVT::i8);
8922 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8924 Chain, Dest, CC, Cmp);
8925 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8951 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8953 Chain, Dest, CC, Cmp);
8954 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8973 CC = NewSetCC.getOperand(0);
8981 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8985 Chain, Dest, CC, Cond);
9266 ISD::CondCode CC = ISD::SETCC_INVALID;
9272 CC = ISD::SETEQ;
9277 CC = ISD::SETLT;
9282 CC = ISD::SETLE;
9287 CC = ISD::SETGT;
9292 CC = ISD::SETGE;
9297 CC = ISD::SETNE;
9302 CC = ISD::SETEQ;
9307 CC = ISD::SETLT;
9312 CC = ISD::SETLE;
9317 CC = ISD::SETGT;
9322 CC = ISD::SETGE;
9327 CC = ISD::SETNE;
9333 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9405 unsigned CC = 0;
9414 CC = 0;
9421 CC = 0;
9428 CC = 1;
9435 CC = 1;
9442 CC = 2;
9449 CC = 2;
9456 CC = 3;
9463 CC = 3;
9470 CC = 4;
9477 CC = 4;
9484 CC = 5;
9491 CC = 5;
9498 CC = 6;
9505 CC = 6;
9512 CC = 7;
9519 CC = 7;
9527 DAG.getConstant(CC, MVT::i8));
9664 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9665 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9918 CallingConv::ID CC = Func->getCallingConv();
9921 switch (CC) {
13297 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13300 // Check for x CC y ? x : y.
13303 switch (CC) {
13365 // Check for x CC y ? y : x -- a min/max with reversed arms.
13368 switch (CC) {
13544 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13545 switch (CC) {
13549 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13591 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13593 if (CC == X86::COND_E || CC == X86::COND_NE) {
13600 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13612 CC = X86::GetOppositeBranchCondition(CC);
13621 DAG.getConstant(CC, MVT::i8), Cond);
13638 DAG.getConstant(CC, MVT::i8), Cond);
13676 DAG.getConstant(CC, MVT::i8), Cond);
15006 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15007 if (CC != X86::COND_E && CC != X86::COND_NE)
15021 if (CC == X86::COND_NE)
15298 AsmPieces[0] == "~{cc}" &&
15316 AsmPieces[0] == "~{cc}" &&
