Lines Matching full:opc
2919 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2921 switch(Opc) {
2926 return DAG.getNode(Opc, dl, VT, V1);
2930 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2933 switch(Opc) {
2940 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2944 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2947 switch(Opc) {
2952 return DAG.getNode(Opc, dl, VT, V1, V2,
2957 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2959 switch(Opc) {
2970 return DAG.getNode(Opc, dl, VT, V1, V2);
4140 unsigned Opc = V2.getOpcode();
4141 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4143 if (Opc != ISD::BUILD_VECTOR ||
4147 unsigned Opc = V1.getOpcode();
4148 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4150 if (Opc != ISD::BUILD_VECTOR ||
4732 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4735 DAG.getNode(Opc, dl, ShVT, SrcOp,
5608 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5616 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6865 unsigned Opc;
6867 Opc = X86ISD::PINSRW;
6869 Opc = X86ISD::PINSRB;
6871 Opc = X86ISD::PINSRB;
6879 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7825 unsigned Opc;
7827 Opc = X86ISD::WIN_FTOL;
7831 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7832 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7833 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7865 if (Opc != X86ISD::WIN_FTOL) {
7868 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8463 unsigned Opc = 0;
8469 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8471 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8473 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8475 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8477 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8484 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8486 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8502 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8513 unsigned Opc = Op.getNode()->getOpcode();
8514 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8517 (Opc == X86ISD::ADD ||
8518 Opc == X86ISD::SUB ||
8519 Opc == X86ISD::ADC ||
8520 Opc == X86ISD::SBB ||
8521 Opc == X86ISD::SMUL ||
8522 Opc == X86ISD::UMUL ||
8523 Opc == X86ISD::INC ||
8524 Opc == X86ISD::DEC ||
8525 Opc == X86ISD::OR ||
8526 Opc == X86ISD::XOR ||
8527 Opc == X86ISD::AND))
8530 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8609 unsigned Opc = Cmp.getOpcode();
8618 Opc == X86ISD::BT) { // FIXME
8706 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8707 Opc = Op.getOpcode();
8708 if (Opc != ISD::OR && Opc != ISD::AND)
8783 unsigned Opc = Cmp.getOpcode();
8785 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9199 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9205 switch (Opc) {
9210 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9215 switch (Opc) {
9217 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9218 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9219 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9231 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9265 unsigned Opc = 0;
9271 Opc = X86ISD::COMI;
9276 Opc = X86ISD::COMI;
9281 Opc = X86ISD::COMI;
9286 Opc = X86ISD::COMI;
9291 Opc = X86ISD::COMI;
9296 Opc = X86ISD::COMI;
9301 Opc = X86ISD::UCOMI;
9306 Opc = X86ISD::UCOMI;
9311 Opc = X86ISD::UCOMI;
9316 Opc = X86ISD::UCOMI;
9321 Opc = X86ISD::UCOMI;
9326 Opc = X86ISD::UCOMI;
9335 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9406 unsigned Opc = 0;
9415 Opc = X86ISD::VPCOM;
9422 Opc = X86ISD::VPCOMU;
9429 Opc = X86ISD::VPCOM;
9436 Opc = X86ISD::VPCOMU;
9443 Opc = X86ISD::VPCOM;
9450 Opc = X86ISD::VPCOMU;
9457 Opc = X86ISD::VPCOM;
9464 Opc = X86ISD::VPCOMU;
9471 Opc = X86ISD::VPCOM;
9478 Opc = X86ISD::VPCOMU;
9485 Opc = X86ISD::VPCOM;
9492 Opc = X86ISD::VPCOMU;
9499 Opc = X86ISD::VPCOM;
9506 Opc = X86ISD::VPCOMU;
9513 Opc = X86ISD::VPCOM;
9520 Opc = X86ISD::VPCOMU;
9526 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
10803 unsigned Opc;
10807 case ISD::ADDC: Opc = X86ISD::ADD; break;
10808 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10809 case ISD::SUBC: Opc = X86ISD::SUB; break;
10810 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10814 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10816 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11726 unsigned Opc;
11729 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11731 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11734 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11736 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11739 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
12209 unsigned Opc =
12211 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12538 unsigned Opc;
12541 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12542 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12543 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12544 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12545 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12546 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12547 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12548 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12549 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12573 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12783 unsigned Opc = Op.getOpcode();
12784 assert((Opc >= ISD::BUILTIN_OP_END ||
12785 Opc == ISD::INTRINSIC_WO_CHAIN ||
12786 Opc == ISD::INTRINSIC_W_CHAIN ||
12787 Opc == ISD::INTRINSIC_VOID) &&
12792 switch (Opc) {
14229 unsigned Opc = X86ISD::SHLD;
14233 Opc = X86ISD::SHRD;
14246 return DAG.getNode(Opc, DL, VT,
14255 return DAG.getNode(Opc, DL, VT,
15136 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15142 switch (Opc) {
