Lines Matching refs:BUILD_VECTOR
826 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
877 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
886 setOperationAction(ISD::BUILD_VECTOR,
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1139 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
4067 if (N->getOpcode() != ISD::BUILD_VECTOR)
4117 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4120 if (N->getOpcode() != ISD::BUILD_VECTOR)
4143 if (Opc != ISD::BUILD_VECTOR ||
4150 if (Opc != ISD::BUILD_VECTOR ||
4170 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4173 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4179 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4185 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4206 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4208 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4215 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4509 if (V.getOpcode() == ISD::BUILD_VECTOR)
4645 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4693 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4817 /// load which has the same value as a build_vector whose operands are 'elts'.
4887 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4908 case ISD::BUILD_VECTOR: {
4909 // The BUILD_VECTOR node must be a splat.
4918 // of its users are from the BUILD_VECTOR node.
5211 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5212 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5643 DAG.getNode(ISD::BUILD_VECTOR, dl,
5663 DAG.getNode(ISD::BUILD_VECTOR, dl,
5799 DAG.getNode(ISD::BUILD_VECTOR, dl,
5816 DAG.getNode(ISD::BUILD_VECTOR, dl,
6203 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6205 // BUILD_VECTOR (load), undef
6660 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
8496 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
9229 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9760 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
10284 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10296 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10309 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10327 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10339 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10352 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10437 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10446 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10448 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10831 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12917 // V UNDEF BUILD_VECTOR UNDEF
12924 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
13007 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13834 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13843 // Handle the case where the build_vector is all undef
13858 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
