Lines Matching refs:EXTRACT_VECTOR_ELT
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
725 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
828 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
877 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
890 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1211 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
5736 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5738 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5848 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5859 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5874 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6723 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6748 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6784 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6804 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6825 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6842 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7656 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7675 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7687 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8027 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
10834 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13183 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13203 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13214 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13881 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
14474 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
15084 case ISD::EXTRACT_VECTOR_ELT:
