Lines Matching refs:ISD
78 if (Vec.getOpcode() == ISD::UNDEF)
79 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
130 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
225 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
236 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
245 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
263 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
264 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
271 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
283 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
288 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
289 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
292 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
294 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
302 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
325 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
330 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
331 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
351 setOperationAction(ISD::MULHS, VT, Expand);
352 setOperationAction(ISD::MULHU, VT, Expand);
353 setOperationAction(ISD::SDIV, VT, Expand);
354 setOperationAction(ISD::UDIV, VT, Expand);
355 setOperationAction(ISD::SREM, VT, Expand);
356 setOperationAction(ISD::UREM, VT, Expand);
359 setOperationAction(ISD::ADDC, VT, Custom);
360 setOperationAction(ISD::ADDE, VT, Custom);
361 setOperationAction(ISD::SUBC, VT, Custom);
362 setOperationAction(ISD::SUBE, VT, Custom);
365 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
366 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
367 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
368 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
374 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f64 , Expand);
377 setOperationAction(ISD::FREM , MVT::f80 , Expand);
378 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
383 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
384 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
385 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
390 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
392 ISD::CTTZ , MVT::i16 , Custom);
393 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
395 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
401 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
402 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
404 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
410 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
411 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
412 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
417 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
423 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
425 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
426 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
427 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
429 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
432 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
433 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
436 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
438 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
439 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
440 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
451 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
452 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
454 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
457 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
458 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
459 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
460 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
462 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
463 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
464 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
466 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
467 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
468 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
469 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
470 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
473 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
474 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
475 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
477 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
478 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
479 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
483 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
485 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
486 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
498 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
499 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
500 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
515 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
522 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
525 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
526 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
527 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
528 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
539 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
540 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
542 setOperationAction(ISD::TRAP, MVT::Other, Legal);
545 setOperationAction(ISD::VASTART , MVT::Other, Custom);
546 setOperationAction(ISD::VAEND , MVT::Other, Expand);
548 setOperationAction(ISD::VAARG , MVT::Other, Custom);
549 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
551 setOperationAction(ISD::VAARG , MVT::Other, Expand);
552 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
555 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
556 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
559 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
562 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
565 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
575 setOperationAction(ISD::FABS , MVT::f64, Custom);
576 setOperationAction(ISD::FABS , MVT::f32, Custom);
579 setOperationAction(ISD::FNEG , MVT::f64, Custom);
580 setOperationAction(ISD::FNEG , MVT::f32, Custom);
583 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
584 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
587 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
588 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
591 setOperationAction(ISD::FSIN , MVT::f64, Expand);
592 setOperationAction(ISD::FCOS , MVT::f64, Expand);
593 setOperationAction(ISD::FSIN , MVT::f32, Expand);
594 setOperationAction(ISD::FCOS , MVT::f32, Expand);
607 setOperationAction(ISD::FABS , MVT::f32, Custom);
610 setOperationAction(ISD::FNEG , MVT::f32, Custom);
612 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
615 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
616 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
619 setOperationAction(ISD::FSIN , MVT::f32, Expand);
620 setOperationAction(ISD::FCOS , MVT::f32, Expand);
630 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
631 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
639 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
640 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
641 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
642 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
645 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
646 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
659 setOperationAction(ISD::FMA, MVT::f64, Expand);
660 setOperationAction(ISD::FMA, MVT::f32, Expand);
665 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
666 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
683 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
684 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
687 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
688 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
689 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
690 setOperationAction(ISD::FRINT, MVT::f80, Expand);
691 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
692 setOperationAction(ISD::FMA, MVT::f80, Expand);
696 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
697 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
698 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
700 setOperationAction(ISD::FLOG, MVT::f80, Expand);
701 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
702 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
703 setOperationAction(ISD::FEXP, MVT::f80, Expand);
704 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
711 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
726 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
729 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
745 ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
763 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
772 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
773 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
774 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
786 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
787 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
788 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
789 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
790 setOperationAction(ISD::AND, MVT::v8i8, Expand);
791 setOperationAction(ISD::AND, MVT::v4i16, Expand);
792 setOperationAction(ISD::AND, MVT::v2i32, Expand);
793 setOperationAction(ISD::AND, MVT::v1i64, Expand);
794 setOperationAction(ISD::OR, MVT::v8i8, Expand);
795 setOperationAction(ISD::OR, MVT::v4i16, Expand);
796 setOperationAction(ISD::OR, MVT::v2i32, Expand);
797 setOperationAction(ISD::OR, MVT::v1i64, Expand);
798 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
799 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
800 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
801 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
806 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
807 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
808 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
809 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
810 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
819 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
820 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
821 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
822 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
823 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
824 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
825 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
826 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
827 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
828 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
829 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
830 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
843 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
844 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
845 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
846 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
848 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
849 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
850 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
851 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
852 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
853 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
854 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
855 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
856 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
857 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
858 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
860 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
861 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
862 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
863 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
886 setOperationAction(ISD::BUILD_VECTOR,
888 setOperationAction(ISD::VECTOR_SHUFFLE,
890 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
903 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
915 setOperationAction(ISD::AND, SVT, Promote);
916 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
917 setOperationAction(ISD::OR, SVT, Promote);
918 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
919 setOperationAction(ISD::XOR, SVT, Promote);
920 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
921 setOperationAction(ISD::LOAD, SVT, Promote);
922 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
923 setOperationAction(ISD::SELECT, SVT, Promote);
924 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
930 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
931 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
932 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
933 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
935 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
936 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
940 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
943 setOperationAction(ISD::FRINT, MVT::f32, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
945 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
946 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
947 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
948 setOperationAction(ISD::FRINT, MVT::f64, Legal);
949 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
952 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
958 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
977 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
983 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
984 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
986 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
987 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
989 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
990 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
993 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
994 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
996 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
997 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
999 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1001 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1002 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1004 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1005 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1007 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1012 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1022 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1024 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1026 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1033 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1038 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1040 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1041 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1042 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1049 setOperationAction(ISD
1051 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1052 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1054 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1055 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1057 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1058 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1063 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1069 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1072 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1076 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1077 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1078 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1080 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1081 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1082 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1083 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1085 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1086 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1087 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1090 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1092 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1093 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1095 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1096 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1098 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1100 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1101 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1102 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1103 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1107 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1110 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1112 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1115 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1119 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1121 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1133 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1139 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1140 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1141 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1143 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1144 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1156 setOperationAction(ISD::AND, SVT, Promote);
1157 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1158 setOperationAction(ISD::OR, SVT, Promote);
1159 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1160 setOperationAction(ISD::XOR, SVT, Promote);
1161 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1162 setOperationAction(ISD::LOAD, SVT, Promote);
1163 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1164 setOperationAction(ISD::SELECT, SVT, Promote);
1165 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1173 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1178 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1190 setOperationAction(ISD::SADDO, VT, Custom);
1191 setOperationAction(ISD::UADDO, VT, Custom);
1192 setOperationAction(ISD::SSUBO, VT, Custom);
1193 setOperationAction(ISD::USUBO, VT, Custom);
1194 setOperationAction(ISD::SMULO, VT, Custom);
1195 setOperationAction(ISD::UMULO, VT, Custom);
1199 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1200 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1210 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1211 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1212 setTargetDAGCombine(ISD::VSELECT);
1213 setTargetDAGCombine(ISD::SELECT);
1214 setTargetDAGCombine(ISD::SHL);
1215 setTargetDAGCombine(ISD::SRA);
1216 setTargetDAGCombine(ISD::SRL);
1217 setTargetDAGCombine(ISD::OR);
1218 setTargetDAGCombine(ISD::AND);
1219 setTargetDAGCombine(ISD::ADD);
1220 setTargetDAGCombine(ISD::FADD);
1221 setTargetDAGCombine(ISD::FSUB);
1222 setTargetDAGCombine(ISD::SUB);
1223 setTargetDAGCombine(ISD::LOAD);
1224 setTargetDAGCombine(ISD::STORE);
1225 setTargetDAGCombine(ISD::ZERO_EXTEND);
1226 setTargetDAGCombine(ISD::SIGN_EXTEND);
1227 setTargetDAGCombine(ISD::TRUNCATE);
1228 setTargetDAGCombine(ISD::SINT_TO_FP);
1230 setTargetDAGCombine(ISD::MUL);
1232 setTargetDAGCombine(ISD::XOR);
1462 const SmallVectorImpl<ISD::OutputArg> &Outs,
1473 const SmallVectorImpl<ISD::OutputArg> &Outs,
1526 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1537 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1538 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1543 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1590 if (Copy->getOpcode() == ISD::CopyToReg) {
1596 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1616 ISD::NodeType ExtendKind) const {
1619 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1634 const SmallVectorImpl<ISD::InputArg> &Ins,
1675 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1703 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1713 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1726 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1763 const SmallVectorImpl<ISD::InputArg> &Ins,
1769 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1805 const SmallVectorImpl<ISD::InputArg> &Ins,
1877 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1880 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1883 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1891 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2005 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2045 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2081 ISD::ArgFlagsTy Flags) const {
2084 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2134 const SmallVectorImpl<ISD::OutputArg> &Outs,
2136 const SmallVectorImpl<ISD::InputArg> &Ins,
2221 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2229 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2232 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2237 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2238 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2241 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2244 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2283 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2372 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2385 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2401 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2434 unsigned WrapperKind = ISD::DELETED_NODE;
2467 if (WrapperKind != ISD::DELETED_NODE)
2639 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2644 if (Arg.getOpcode() == ISD::CopyFromReg) {
2676 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2698 const SmallVectorImpl<ISD::OutputArg> &Outs,
2700 const SmallVectorImpl<ISD::InputArg> &Ins,
2836 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2886 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2890 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3044 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3047 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3051 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3055 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3058 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3067 case ISD::SETEQ: return X86::COND_E;
3068 case ISD::SETGT: return X86::COND_G;
3069 case ISD::SETGE: return X86::COND_GE;
3070 case ISD::SETLT: return X86::COND_L;
3071 case ISD::SETLE: return X86::COND_LE;
3072 case ISD::SETNE: return X86::COND_NE;
3073 case ISD::SETULT: return X86::COND_B;
3074 case ISD::SETUGT: return X86::COND_A;
3075 case ISD::SETULE: return X86::COND_BE;
3076 case ISD::SETUGE: return X86::COND_AE;
3083 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3084 !ISD
3091 case ISD::SETOLT:
3092 case ISD::SETOLE:
3093 case ISD::SETUGT:
3094 case ISD::SETUGE:
3107 case ISD::SETUEQ:
3108 case ISD::SETEQ: return X86::COND_E;
3109 case ISD::SETOLT: // flipped
3110 case ISD::SETOGT:
3111 case ISD::SETGT: return X86::COND_A;
3112 case ISD::SETOLE: // flipped
3113 case ISD::SETOGE:
3114 case ISD::SETGE: return X86::COND_AE;
3115 case ISD::SETUGT: // flipped
3116 case ISD::SETULT:
3117 case ISD::SETLT: return X86::COND_B;
3118 case ISD::SETUGE: // flipped
3119 case ISD::SETULE:
3120 case ISD::SETLE: return X86::COND_BE;
3121 case ISD::SETONE:
3122 case ISD::SETNE: return X86::COND_NE;
3123 case ISD::SETUO: return X86::COND_P;
3124 case ISD::SETO: return X86::COND_NP;
3125 case ISD::SETOEQ:
3126 case ISD::SETUNE: return X86::COND_INVALID;
4054 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4057 if (!ISD::isNON_EXTLoad(N))
4067 if (N->getOpcode() != ISD::BUILD_VECTOR)
4073 case ISD::UNDEF:
4074 case ISD::ConstantFP:
4075 case ISD::Constant:
4083 return !ISD::isBuildVectorAllZeros(N) &&
4084 !ISD::isBuildVectorAllOnes(N);
4097 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4101 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4120 if (N->getOpcode() != ISD::BUILD_VECTOR)
4141 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4143 if (Opc != ISD::BUILD_VECTOR ||
4148 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4150 if (Opc != ISD::BUILD_VECTOR ||
4170 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4173 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4179 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4185 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4188 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4206 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4208 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4209 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4215 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4218 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4297 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4308 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4313 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4462 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4496 if (Opcode == ISD::BITCAST) {
4505 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4509 if (V.getOpcode() == ISD::BUILD_VECTOR)
4526 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4672 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4676 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4677 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4680 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4685 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4690 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4716 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4733 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4734 return DAG.getNode(ISD::BITCAST, dl, VT,
4749 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4794 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4839 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4842 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4848 if (Elt.getOpcode() == ISD::UNDEF)
4880 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4908 case ISD::BUILD_VECTOR: {
4914 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4915 Ld.getOpcode() == ISD::ConstantFP);
4925 case ISD::VECTOR_SHUFFLE: {
4934 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4938 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4939 Ld.getOpcode() == ISD::ConstantFP);
4983 if (!ISD::isNormalLoad(Ld.getNode()))
5025 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5037 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5057 if (Elt.getOpcode() == ISD::UNDEF)
5060 if (Elt.getOpcode() != ISD::Constant &&
5061 Elt.getOpcode() != ISD::ConstantFP)
5095 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5096 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5110 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5120 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5126 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5130 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5136 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5137 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5146 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5156 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5170 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5211 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5212 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5216 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5227 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5255 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5300 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5301 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5306 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5307 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5317 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5318 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5335 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5357 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5360 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5362 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5363 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5366 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5371 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5386 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5482 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5483 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5486 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5569 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5570 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5571 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5641 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5643 DAG.getNode(ISD::BUILD_VECTOR, dl,
5646 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5661 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5663 DAG.getNode(ISD::BUILD_VECTOR, dl,
5665 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5666 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5686 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5710 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5736 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5738 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5740 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5799 DAG.getNode(ISD::BUILD_VECTOR, dl,
5816 DAG.getNode(ISD::BUILD_VECTOR, dl,
5818 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5824 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5825 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5848 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5850 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5859 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5862 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5866 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5874 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5877 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5881 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5883 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5886 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5889 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5933 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5934 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5952 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5953 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5957 return DAG.getNode(ISD::BITCAST, dl, VT,
5959 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5967 return DAG.getNode(ISD::BITCAST, dl, VT,
5969 DAG.getNode(ISD::BITCAST, dl,
6052 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shufs[0],
6199 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6201 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6203 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6204 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6220 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6222 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6224 if (ISD::isNormalLoad(V.getNode()))
6234 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6235 return DAG.getNode(ISD::BITCAST, dl, VT,
6253 return DAG.getNode(ISD::BITCAST, dl, VT,
6255 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6256 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6268 if (V2.getOpcode() == ISD::UNDEF)
6367 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6372 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6381 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6402 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6403 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6494 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6660 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6664 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6715 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6717 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6722 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6723 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6724 DAG.getNode(ISD::BITCAST, dl,
6730 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6732 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6742 if ((User->getOpcode() != ISD::STORE ||
6745 (User->getOpcode() != ISD::BITCAST ||
6748 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6749 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6752 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6784 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6803 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6804 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6805 DAG.getNode(ISD::BITCAST, dl,
6812 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6814 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6825 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6842 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6876 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6891 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6925 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6942 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6964 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6967 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6974 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6976 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6979 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6980 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7051 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7084 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7124 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7158 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7193 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7207 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7246 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7260 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7268 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7312 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7366 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7371 // Lowering the machine isd will make sure everything is in the right
7425 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7434 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7436 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7448 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7462 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7466 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7471 if (Op.getOpcode() == ISD::SHL_PARTS) {
7473 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7476 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7479 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7489 if (Op.getOpcode() == ISD::SHL_PARTS) {
7628 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7634 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7640 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7641 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7648 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7651 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7652 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7656 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7669 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7675 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7676 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7680 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7681 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7682 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7684 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7685 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7687 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7688 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7692 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7698 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7701 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7717 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7733 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7770 ISD::SETLT);
7780 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7782 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7786 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7790 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7791 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7881 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7970 return DAG.getNode(ISD::BITCAST, dl, VT,
7971 DAG.getNode(ISD::XOR, dl, XORVT,
7972 DAG.getNode(ISD::BITCAST, dl, XORVT,
7974 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7990 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7995 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8023 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8026 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8027 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8058 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8061 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8098 case ISD::ADD:
8111 if (UI->getOpcode() != ISD::CopyToReg &&
8112 UI->getOpcode() != ISD::SETCC &&
8113 UI->getOpcode() != ISD::STORE)
8137 case ISD::AND: {
8145 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8151 if (User->getOpcode() != ISD::BRCOND &&
8152 User->getOpcode() != ISD::SETCC &&
8153 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8163 case ISD::SUB:
8164 case ISD::OR:
8165 case ISD::XOR:
8170 if (UI->getOpcode() == ISD::STORE)
8176 case ISD::SUB: Opcode = X86ISD::SUB; break;
8177 case ISD::OR: Opcode = X86ISD::OR; break;
8178 case ISD::XOR: Opcode = X86ISD::XOR; break;
8179 case ISD::AND: Opcode = X86ISD::AND; break;
8226 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8230 if (Op0.getOpcode() == ISD::TRUNCATE)
8232 if (Op1.getOpcode() == ISD::TRUNCATE)
8236 if (Op1.getOpcode() == ISD::SHL)
8238 if (Op0.getOpcode() == ISD::SHL) {
8254 } else if (Op1.getOpcode() == ISD::Constant) {
8259 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8279 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8284 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8287 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8303 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8309 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8310 Op1.getOpcode() == ISD::Constant &&
8312 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8320 if (Op1.getOpcode() == ISD::Constant &&
8323 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8329 bool Invert = (CC == ISD::SETNE) ^
8354 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8376 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8388 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8410 case ISD::SETOEQ:
8411 case ISD::SETEQ: SSECC = 0; break;
8412 case ISD::SETOGT:
8413 case ISD::SETGT: Swap = true; // Fallthrough
8414 case ISD::SETLT:
8415 case ISD::SETOLT: SSECC = 1; break;
8416 case ISD::SETOGE:
8417 case ISD::SETGE: Swap = true; // Fallthrough
8418 case ISD::SETLE:
8419 case ISD::SETOLE: SSECC = 2; break;
8420 case ISD::SETUO: SSECC = 3; break;
8421 case ISD::SETUNE:
8422 case ISD::SETNE: SSECC = 4; break;
8423 case ISD::SETULE: Swap = true;
8424 case ISD::SETUGE: SSECC = 5; break;
8425 case ISD::SETULT: Swap = true;
8426 case ISD::SETUGT: SSECC = 6; break;
8427 case ISD::SETO: SSECC = 7; break;
8434 if (SetCCOpcode == ISD::SETUEQ) {
8440 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8441 } else if (SetCCOpcode == ISD::SETONE) {
8447 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8468 case ISD::SETNE: Invert = true;
8469 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8470 case ISD::SETLT: Swap = true;
8471 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8472 case ISD::SETGE: Swap = true;
8473 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8474 case ISD::SETULT: Swap = true;
8475 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8476 case ISD::SETUGE: Swap = true;
8477 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8496 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8498 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8499 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8554 if (Cond.getOpcode() == ISD::SETCC) {
8588 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8594 if (Cond.getOpcode() == ISD::AND &&
8622 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8623 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8624 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8632 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8633 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8634 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8635 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8636 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8637 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8640 if (CondOpcode == ISD::UMULO)
8648 if (CondOpcode == ISD::UMULO)
8659 if (Cond.getOpcode() == ISD::TRUNCATE)
8664 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8665 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8703 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8704 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8708 if (Opc != ISD::OR && Opc != ISD::AND)
8716 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8719 if (Op.getOpcode() != ISD::XOR)
8738 if (Cond.getOpcode() == ISD::SETCC) {
8740 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8744 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8745 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8746 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8747 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8748 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8749 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8768 if (Cond.getOpcode() == ISD::AND &&
8802 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8803 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8804 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8812 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8813 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8814 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8815 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8816 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8817 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8822 if (CondOpcode == ISD::UMULO)
8830 if (CondOpcode == ISD::UMULO)
8841 if (CondOpc == ISD::OR) {
8854 } else { // ISD::AND
8871 if (User->getOpcode() == ISD::BR) {
8900 } else if (Cond.getOpcode() == ISD::SETCC &&
8901 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8912 if (User->getOpcode() == ISD::BR) {
8930 } else if (Cond.getOpcode() == ISD::SETCC &&
8931 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8942 if (User->getOpcode() == ISD::BR) {
8965 if (Cond.getOpcode() == ISD::TRUNCATE)
8970 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8971 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9085 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9094 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9104 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9111 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9229 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9230 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9266 ISD::CondCode CC = ISD::SETCC_INVALID;
9272 CC = ISD::SETEQ;
9277 CC = ISD::SETLT;
9282 CC = ISD::SETLE;
9287 CC = ISD::SETGT;
9292 CC = ISD::SETGE;
9297 CC = ISD::SETNE;
9302 CC = ISD::SETEQ;
9307 CC = ISD::SETLT;
9312 CC = ISD::SETLE;
9317 CC = ISD::SETGT;
9322 CC = ISD::SETGE;
9327 CC = ISD::SETNE;
9338 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9563 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9569 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9573 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9666 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9760 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9765 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9766 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9787 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9831 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9833 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9878 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9887 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9893 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9901 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9908 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9914 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9963 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9965 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9975 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9982 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9988 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9994 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10046 DAG.getNode(ISD::SRL, DL, MVT::i16,
10047 DAG.getNode(ISD::AND, DL, MVT::i16,
10051 DAG.getNode(ISD::SRL, DL, MVT::i16,
10052 DAG.getNode(ISD::AND, DL, MVT::i16,
10057 DAG.getNode(ISD::AND, DL, MVT::i16,
10058 DAG.getNode(ISD::ADD, DL, MVT::i16,
10059 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10065 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10078 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10095 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10098 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10113 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10121 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10124 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10174 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10226 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10227 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10228 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10229 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10238 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10239 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10262 if (Op.getOpcode() == ISD::SHL)
10265 if (Op.getOpcode() == ISD::SRL)
10268 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10274 if (Op.getOpcode() == ISD::SHL) {
10278 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10283 return DAG.getNode(ISD::AND, dl, VT, SHL,
10284 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10286 if (Op.getOpcode() == ISD::SRL) {
10290 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10295 return DAG.getNode(ISD::AND, dl, VT, SRL,
10296 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10298 if (Op.getOpcode() == ISD::SRA) {
10306 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10309 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10310 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10311 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10317 if (Op.getOpcode() == ISD::SHL) {
10321 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10326 return DAG.getNode(ISD::AND, dl, VT, SHL,
10327 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10329 if (Op.getOpcode() == ISD::SRL) {
10333 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10338 return DAG.getNode(ISD::AND, dl, VT, SRL,
10339 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10341 if (Op.getOpcode() == ISD::SRA) {
10349 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10352 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10353 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10354 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10362 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10373 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10374 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10375 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10376 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10378 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10384 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10388 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10395 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10398 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10399 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10402 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10403 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10407 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10410 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10411 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10414 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10415 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10419 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10420 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10437 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10446 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10448 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10462 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10481 case ISD::SADDO:
10493 case ISD::UADDO:
10497 case ISD::SSUBO:
10509 case ISD::USUBO:
10513 case ISD::SMULO:
10517 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10527 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10540 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10585 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10723 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10726 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10757 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10759 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10781 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10807 case ISD::ADDC: Opc = X86ISD::ADD; break;
10808 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10809 case ISD::SUBC: Opc = X86ISD::SUB; break;
10810 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10825 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10826 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10827 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10828 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10829 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10830 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10831 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10832 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10833 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10834 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10835 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10836 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10837 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10838 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10839 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10840 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10841 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10842 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10843 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10844 case ISD::SHL_PARTS:
10845 case ISD::SRA_PARTS:
10846 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10847 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10848 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10849 case ISD
10850 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10851 case ISD::FABS: return LowerFABS(Op, DAG);
10852 case ISD::FNEG: return LowerFNEG(Op, DAG);
10853 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10854 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10855 case ISD::SETCC: return LowerSETCC(Op, DAG);
10856 case ISD::SELECT: return LowerSELECT(Op, DAG);
10857 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10858 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10859 case ISD::VASTART: return LowerVASTART(Op, DAG);
10860 case ISD::VAARG: return LowerVAARG(Op, DAG);
10861 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10862 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10863 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10864 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10865 case ISD::FRAME_TO_ARGS_OFFSET:
10867 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10868 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10869 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10870 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10871 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10872 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10873 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10874 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10875 case ISD::MUL: return LowerMUL(Op, DAG);
10876 case ISD::SRA:
10877 case ISD::SRL:
10878 case ISD::SHL: return LowerShift(Op, DAG);
10879 case ISD::SADDO:
10880 case ISD::UADDO:
10881 case ISD::SSUBO:
10882 case ISD::USUBO:
10883 case ISD::SMULO:
10884 case ISD::UMULO: return LowerXALUO(Op, DAG);
10885 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10886 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10887 case ISD::ADDC:
10888 case ISD::ADDE:
10889 case ISD::SUBC:
10890 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10891 case ISD::ADD: return LowerADD(Op, DAG);
10892 case ISD::SUB: return LowerSUB(Op, DAG);
10907 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10926 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10928 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10936 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10949 case ISD::SIGN_EXTEND_INREG:
10950 case ISD::ADDC:
10951 case ISD::ADDE:
10952 case ISD::SUBC:
10953 case ISD::SUBE:
10956 case ISD::FP_TO_SINT:
10957 case ISD::FP_TO_UINT: {
10958 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10978 case ISD::READCYCLECOUNTER: {
10988 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10992 case ISD::ATOMIC_CMP_SWAP: {
10998 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11000 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11009 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11011 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11035 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11039 case ISD::ATOMIC_LOAD_ADD:
11042 case ISD::ATOMIC_LOAD_AND:
11045 case ISD::ATOMIC_LOAD_NAND:
11048 case ISD::ATOMIC_LOAD_OR:
11051 case ISD::ATOMIC_LOAD_SUB:
11054 case ISD::ATOMIC_LOAD_XOR:
11057 case ISD::ATOMIC_SWAP:
11060 case ISD::ATOMIC_LOAD:
12784 assert((Opc >= ISD::BUILTIN_OP_END ||
12785 Opc == ISD::INTRINSIC_WO_CHAIN ||
12786 Opc == ISD::INTRINSIC_W_CHAIN ||
12787 Opc == ISD::INTRINSIC_VOID) &&
12812 case ISD::INTRINSIC_WO_CHAIN: {
12912 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12913 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12924 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12925 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12926 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12929 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12951 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12970 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12978 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
13000 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13036 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13039 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13042 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13043 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13060 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13063 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13066 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13067 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13080 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13081 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13087 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13111 if (InVec.getOpcode() == ISD::BITCAST) {
13144 if (LdNode.getOpcode() == ISD::BITCAST) {
13153 if (!ISD::isNormalLoad(LdNode.getNode()))
13169 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13182 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13183 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13214 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13221 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13222 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13259 SDValue ScalarAddr = DAG.getNode(ISD
13293 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13297 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13305 case ISD::SETULT:
13317 case ISD::SETOLE:
13325 case ISD::SETULE:
13329 case ISD::SETOLT:
13330 case ISD::SETLT:
13331 case ISD::SETLE:
13335 case ISD::SETOGE:
13343 case ISD::SETUGT:
13355 case ISD::SETUGE:
13359 case ISD::SETOGT:
13360 case ISD::SETGT:
13361 case ISD::SETGE:
13370 case ISD::SETOGE:
13382 case ISD::SETUGT:
13389 case ISD::SETUGE:
13393 case ISD::SETOGT:
13394 case ISD::SETGT:
13395 case ISD::SETGE:
13399 case ISD::SETULT:
13405 case ISD::SETOLE:
13417 case ISD::SETULE:
13421 case ISD::SETOLT:
13422 case ISD::SETLT:
13423 case ISD::SETLE:
13445 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13446 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13456 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13460 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13463 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13470 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13474 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13476 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13505 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13509 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13513 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13518 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13541 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13544 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13547 case ISD::SETLT:
13548 case ISD::SETGT: {
13549 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13552 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13562 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13564 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13624 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13627 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13641 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13643 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13678 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13682 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13687 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13736 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13744 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13751 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13772 N1C && N0.getOpcode() == ISD::AND &&
13773 N0.getOperand(1).getOpcode() == ISD::Constant) {
13776 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13777 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13783 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13800 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13813 if (N->getOpcode() == ISD::SHL) {
13834 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13839 if (Arg.getOpcode() == ISD::UNDEF) continue;
13850 if (Arg.getOpcode() == ISD::UNDEF) continue;
13855 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13858 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13863 if (Arg.getOpcode() == ISD::UNDEF) continue;
13867 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13881 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13889 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13891 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13898 case ISD::SHL:
13909 case ISD::SRA:
13918 case ISD::SRL:
13966 case ISD::BR_CC:
13967 case ISD::BRCOND:
13968 case ISD::SELECT:
13971 case ISD::CopyToReg:
13972 case ISD::SIGN_EXTEND:
13973 case ISD::ZERO_EXTEND:
13974 case ISD::ANY_EXTEND:
13998 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14000 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14002 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14017 if (ISD::isBuildVectorAllOnes(N))
14021 if (N->getOpcode() == ISD::BITCAST)
14027 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14031 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14032 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14033 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14034 ISD::isBuildVectorAllOnes(V2.getNode()))
14062 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14065 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14069 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14074 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14079 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14084 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14103 if (N0.getOpcode() == ISD::XOR &&
14104 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14109 if (N1.getOpcode() == ISD::XOR &&
14110 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14142 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14157 if (Mask.getOpcode() == ISD::BITCAST)
14159 if (X.getOpcode() == ISD::BITCAST)
14161 if (Y.getOpcode() == ISD::BITCAST)
14184 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14185 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14190 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14198 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14199 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14200 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14201 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14202 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14210 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14212 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14223 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14225 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14232 if (ShAmt0.getOpcode() == ISD::SUB) {
14239 if (ShAmt1.getOpcode() == ISD::SUB) {
14243 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14248 DAG.getNode(ISD::TRUNCATE, DL,
14257 DAG.getNode(ISD::TRUNCATE, DL,
14283 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14287 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14303 ISD::LoadExtType Ext = Ld->getExtensionType();
14310 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14352 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14357 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14370 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14395 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14403 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14411 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14440 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14466 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14474 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14480 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14484 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14518 ChainVal->getOpcode() == ISD::TokenFactor) {
14528 if (!Ld || !ISD::isNormalLoad(Ld))
14551 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14562 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14579 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14584 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14596 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14627 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14628 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14653 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14654 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14656 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14661 if (LHS.getOpcode() != ISD::UNDEF)
14671 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14672 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14674 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14679 if (RHS.getOpcode() != ISD::UNDEF)
14805 if (Op.getOpcode() == ISD::BITCAST)
14811 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14861 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14871 // ISD::SETCC is always legalized to i8.
14877 if (N0.getOpcode() == ISD::AND &&
14886 return DAG.getNode(ISD::AND, dl, VT,
14915 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14916 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14918 ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14936 return DAG.getNode(ISD::AND, DL, MVT::i8,
14949 if (Op0.getOpcode() == ISD::LOAD) {
14953 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14979 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14998 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14999 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15020 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15022 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15025 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15057 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15061 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15064 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15084 case ISD::EXTRACT_VECTOR_ELT:
15086 case ISD::VSELECT:
15087 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15089 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15090 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15092 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15093 case ISD::SHL:
15094 case ISD::SRA:
15095 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15096 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15097 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15098 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15099 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15100 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15101 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15102 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15103 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15109 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
15110 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15111 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15126 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15145 case ISD::LOAD:
15146 case ISD::SIGN_EXTEND:
15147 case ISD::ZERO_EXTEND:
15148 case ISD::ANY_EXTEND:
15149 case ISD::SHL:
15150 case ISD::SRL:
15151 case ISD::SUB:
15152 case ISD::ADD:
15153 case ISD::MUL:
15154 case ISD::AND:
15155 case ISD::OR:
15156 case ISD::XOR:
15173 case ISD::LOAD: {
15177 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15183 if (UI->getOpcode() != ISD::CopyToReg)
15190 case ISD::SIGN_EXTEND:
15191 case ISD::ZERO_EXTEND:
15192 case ISD::ANY_EXTEND:
15195 case ISD::SHL:
15196 case ISD::SRL: {
15204 case ISD::ADD:
15205 case ISD::MUL:
15206 case ISD::AND:
15207 case ISD::OR:
15208 case ISD::XOR:
15211 case ISD::SUB: {
15604 } else if (Op.getOpcode() == ISD::ADD) {
15610 } else if (Op.getOpcode() == ISD::SUB) {
