Lines Matching refs:SETCC
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
444 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
452 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
752 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
830 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
860 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
861 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
862 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
863 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
1012 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1063 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
8106 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8112 UI->getOpcode() != ISD::SETCC &&
8152 User->getOpcode() != ISD::SETCC &&
8288 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8299 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8325 // If the input is a setcc, then reuse the input setcc or use a new one with
8327 if (Op0.getOpcode() == X86ISD::SETCC) {
8334 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8345 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8354 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8554 if (Cond.getOpcode() == ISD::SETCC) {
8564 if (Cond.getOpcode() == X86ISD::SETCC &&
8602 // setting operand in place of the X86ISD::SETCC.
8604 if (CondOpcode == X86ISD::SETCC ||
8704 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8710 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8712 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8716 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8717 // 1 and that the SETCC node has a single use.
8723 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8738 if (Cond.getOpcode() == ISD::SETCC) {
8739 // Check for setcc([su]{add,sub,mul}o == 0).
8776 // setting operand in place of the X86ISD::SETCC.
8778 if (CondOpcode == X86ISD::SETCC ||
8891 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8900 } else if (Cond.getOpcode() == ISD::SETCC &&
8930 } else if (Cond.getOpcode() == ISD::SETCC &&
9336 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9338 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9605 // or testp pattern and a setcc for the result.
9665 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9666 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10470 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10471 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10522 SDValue SetCC =
10523 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10527 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10535 SDValue SetCC =
10536 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10540 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10855 case ISD::SETCC: return LowerSETCC(Op, DAG);
11089 case X86ISD::SETCC: return "X86ISD::SETCC";
12809 case X86ISD::SETCC:
13293 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13445 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13467 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13541 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13616 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13620 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13634 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13637 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13675 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13933 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14871 // ISD::SETCC is always legalized to i8.
14926 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15002 SDValue SetCC = Ext.getOperand(0);
15003 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15006 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15010 SDValue Cmp = SetCC.getOperand(1);
15112 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
