Lines Matching refs:SRL
472 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
748 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
983 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
984 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
993 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
994 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1001 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1002 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1051 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1052 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1092 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1093 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1115 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1216 setTargetDAGCombine(ISD::SRL);
5877 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
7476 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8259 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9569 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
10046 DAG.getNode(ISD::SRL, DL, MVT::i16,
10051 DAG.getNode(ISD::SRL, DL, MVT::i16,
10253 // Optimize shl/srl/sra with constant shift amount.
10265 if (Op.getOpcode() == ISD::SRL)
10286 if (Op.getOpcode() == ISD::SRL) {
10288 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10290 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10295 return DAG.getNode(ISD::AND, dl, VT, SRL,
10306 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10329 if (Op.getOpcode() == ISD::SRL) {
10331 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10333 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10338 return DAG.getNode(ISD::AND, dl, VT, SRL,
10349 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10877 case ISD::SRL:
13918 case ISD::SRL:
14210 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14212 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
15095 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15150 case ISD::SRL:
15196 case ISD::SRL: {
