Lines Matching refs:UNDEF
77 // Extract from UNDEF is UNDEF.
78 if (Vec.getOpcode() == ISD::UNDEF)
79 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
612 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
639 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
640 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
665 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
3160 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3166 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3176 /// sequential range (L, L+Pos]. or is undef.
3202 // Lower quadword copied in order or undef.
3255 // Lane is all undef, go to next lane
3394 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3530 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3573 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4073 case ISD::UNDEF:
4141 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4148 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4209 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4360 /// vector of zero or undef vector. This produces a shuffle where the low
4361 /// element of V2 is swizzled into the zero/undef vector, landing at element
4526 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4545 // Ignore undef indicies
4819 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4822 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4832 // For each element in the initializer, see if we've found a load or an undef.
4839 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4842 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4848 if (Elt.getOpcode() == ISD::UNDEF)
5057 if (Elt.getOpcode() == ISD::UNDEF)
5071 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5075 // Special case for single non-zero, non-undef, element.
5185 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5187 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5216 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5225 // One half is zero or undef.
5300 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5306 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5314 // our (non-undef) elements to the full vector width with the element in the
5317 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5330 // If V[i+EltStride] is undef and this is the first round of mixing,
5333 // inserted as undef can be dropped. This isn't safe for successive
5335 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5386 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5504 // of the result come from the same quadword of one of the two inputs. Undef
5780 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5831 // This word of the result is all undef, skip it.
6052 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shufs[0],
6204 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6205 // BUILD_VECTOR (load), undef
6268 if (V2.getOpcode() == ISD::UNDEF)
6402 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6403 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6417 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6538 // Canonicalize the splat or undef, if present, to be on the RHS.
6547 // Shuffling low element of v1 into undef, just return v1.
6967 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
12917 // V UNDEF BUILD_VECTOR UNDEF
12925 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12926 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12970 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12978 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
13839 if (Arg.getOpcode() == ISD::UNDEF) continue;
13843 // Handle the case where the build_vector is all undef
13850 if (Arg.getOpcode() == ISD::UNDEF) continue;
13863 if (Arg.getOpcode() == ISD::UNDEF) continue;
14032 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14307 // TODO: It is possible to support ZExt by zeroing the undef values
14615 /// operands is UNDEF then the result is UNDEF.
14648 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14649 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14654 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14656 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14661 if (LHS.getOpcode() != ISD::UNDEF)
14672 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14674 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14679 if (RHS.getOpcode() != ISD::UNDEF)
14689 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14705 // Ignore any UNDEF components.
14721 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14722 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
