Lines Matching refs:ZERO_EXTEND
765 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
1225 setTargetDAGCombine(ISD::ZERO_EXTEND);
1619 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2232 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
4672 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4676 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5136 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
9338 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9666 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10065 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10078 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10113 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
13222 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13460 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13474 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13509 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13624 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13641 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13678 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13777 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13891 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13973 case ISD::ZERO_EXTEND:
14999 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15109 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
15147 case ISD::ZERO_EXTEND:
15191 case ISD::ZERO_EXTEND:
