Lines Matching full:port1
22 def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
26 [ Port0, Port1 ],
35 // Default is 1 cycle, port0 or port1
36 InstrItinData<IIC_DEFAULT, [InstrStage<1, [Port0, Port1]>] >,
38 InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
39 InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
40 InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
42 InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
43 InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
44 InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
45 InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
46 InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
47 InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >,
49 InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >,
50 InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
51 InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
52 InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
53 InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
54 InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >,
56 InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >,
57 InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >,
60 InstrItinData<IIC_IMUL64_RM, [InstrStage<12, [Port0, Port1]>] >,
61 InstrItinData<IIC_IMUL64_RR, [InstrStage<12, [Port0, Port1]>] >,
63 InstrItinData<IIC_IMUL16_RRI, [InstrStage<6, [Port0, Port1]>] >,
65 InstrItinData<IIC_IMUL64_RRI, [InstrStage<14, [Port0, Port1]>] >,
66 InstrItinData<IIC_IMUL16_RMI, [InstrStage<7, [Port0, Port1]>] >,
68 InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >,
70 InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >,
71 InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >,
72 InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >,
73 InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >,
75 InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >,
76 InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >,
77 InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >,
78 InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >,
79 InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >,
81 InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >,
84 InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
89 InstrItinData<IIC_SHD16_REG_IM, [InstrStage<6, [Port0, Port1]>] >,
90 InstrItinData<IIC_SHD16_REG_CL, [InstrStage<6, [Port0, Port1]>] >,
91 InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<6, [Port0, Port1]>] >,
92 InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<6, [Port0, Port1]>] >,
93 InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [Port0, Port1]>] >,
94 InstrItinData<IIC_SHD32_REG_CL, [InstrStage<2, [Port0, Port1]>] >,
95 InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<4, [Port0, Port1]>] >,
96 InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [Port0, Port1]>] >,
97 InstrItinData<IIC_SHD64_REG_IM, [InstrStage<9, [Port0, Port1]>] >,
98 InstrItinData<IIC_SHD64_REG_CL, [InstrStage<8, [Port0, Port1]>] >,
99 InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<9, [Port0, Port1]>] >,
100 InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<9, [Port0, Port1]>] >,
103 InstrItinData<IIC_CMOV16_RR, [InstrStage<1, [Port0, Port1]>] >,
105 InstrItinData<IIC_CMOV32_RR, [InstrStage<1, [Port0, Port1]>] >,
107 InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
109 InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
110 InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
112 InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,
114 InstrItinData<IIC_JCXZ, [InstrStage<4, [Port0, Port1]>] >,
116 InstrItinData<IIC_JMP_REL, [InstrStage<1, [Port1]>] >,
118 InstrItinData<IIC_JMP_REG, [InstrStage<1, [Port1]>] >,
119 InstrItinData<IIC_JMP_MEM, [InstrStage<2, [Port0, Port1]>] >,
121 InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<32, [Port0, Port1]>] >,
122 InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<31, [Port0, Port1]>] >,
124 InstrItinData<IIC_LOOP, [InstrStage<18, [Port0, Port1]>] >,
125 InstrItinData<IIC_LOOPE, [InstrStage<8, [Port0, Port1]>] >,
126 InstrItinData<IIC_LOOPNE, [InstrStage<17, [Port0, Port1]>] >,
129 InstrStage<1, [Port1]>] >,
130 InstrItinData<IIC_CALL_MEM, [InstrStage<15, [Port0, Port1]>] >,
131 InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<40, [Port0, Port1]>] >,
132 InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<39, [Port0, Port1]>] >,
134 InstrItinData<IIC_RET, [InstrStage<79, [Port0, Port1]>] >,
135 InstrItinData<IIC_RET_IMM, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
138 InstrItinData<IIC_MOVSX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
139 InstrItinData<IIC_MOVSX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
140 InstrItinData<IIC_MOVSX_R16_R16, [InstrStage<1, [Port0, Port1]>] >,
141 InstrItinData<IIC_MOVSX_R32_R32, [InstrStage<1, [Port0, Port1]>] >,
144 InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
145 InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
147 InstrItinData<IIC_REP_MOVS, [InstrStage<75, [Port0, Port1]>] >,
148 InstrItinData<IIC_REP_STOS, [InstrStage<74, [Port0, Port1]>] >,
152 InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<5, [Port1]>] >,
154 InstrStage<5, [Port1]>] >,
155 InstrItinData<IIC_SSE_ALU_F64S_RR, [InstrStage<5, [Port1]>] >,
157 InstrStage<5, [Port1]>] >,
162 InstrItinData<IIC_SSE_DIV_F32S_RR, [InstrStage<34, [Port0, Port1]>] >,
163 InstrItinData<IIC_SSE_DIV_F32S_RM, [InstrStage<34, [Port0, Port1]>] >,
164 InstrItinData<IIC_SSE_DIV_F64S_RR, [InstrStage<62, [Port0, Port1]>] >,
165 InstrItinData<IIC_SSE_DIV_F64S_RM, [InstrStage<62, [Port0, Port1]>] >,
167 InstrItinData<IIC_SSE_COMIS_RR, [InstrStage<9, [Port0, Port1]>] >,
168 InstrItinData<IIC_SSE_COMIS_RM, [InstrStage<10, [Port0, Port1]>] >,
170 InstrItinData<IIC_SSE_HADDSUB_RR, [InstrStage<8, [Port0, Port1]>] >,
171 InstrItinData<IIC_SSE_HADDSUB_RM, [InstrStage<9, [Port0, Port1]>] >,
174 InstrItinData<IIC_SSE_ALU_F32P_RR, [InstrStage<5, [Port1]>] >,
176 InstrStage<5, [Port1]>] >,
177 InstrItinData<IIC_SSE_ALU_F64P_RR, [InstrStage<6, [Port0, Port1]>] >,
178 InstrItinData<IIC_SSE_ALU_F64P_RM, [InstrStage<7, [Port0, Port1]>] >,
181 InstrItinData<IIC_SSE_MUL_F64P_RR, [InstrStage<9, [Port0, Port1]>] >,
182 InstrItinData<IIC_SSE_MUL_F64P_RM, [InstrStage<10, [Port0, Port1]>] >,
183 InstrItinData<IIC_SSE_DIV_F32P_RR, [InstrStage<70, [Port0, Port1]>] >,
184 InstrItinData<IIC_SSE_DIV_F32P_RM, [InstrStage<70, [Port0, Port1]>] >,
185 InstrItinData<IIC_SSE_DIV_F64P_RR, [InstrStage<125, [Port0, Port1]>] >,
186 InstrItinData<IIC_SSE_DIV_F64P_RM, [InstrStage<125, [Port0, Port1]>] >,
189 InstrItinData<IIC_SSE_BIT_P_RR, [InstrStage<1, [Port0, Port1]>] >,
193 InstrItinData<IIC_SSE_INTALU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
195 InstrItinData<IIC_SSE_INTALUQ_P_RR, [InstrStage<2, [Port0, Port1]>] >,
196 InstrItinData<IIC_SSE_INTALUQ_P_RM, [InstrStage<3, [Port0, Port1]>] >,
203 InstrItinData<IIC_SSE_INTSH_P_RR, [InstrStage<2, [Port0, Port1]>] >,
204 InstrItinData<IIC_SSE_INTSH_P_RM, [InstrStage<3, [Port0, Port1]>] >,
205 InstrItinData<IIC_SSE_INTSH_P_RI, [InstrStage<1, [Port0, Port1]>] >,
207 InstrItinData<IIC_SSE_CMPP_RR, [InstrStage<6, [Port0, Port1]>] >,
208 InstrItinData<IIC_SSE_CMPP_RM, [InstrStage<7, [Port0, Port1]>] >,
215 InstrItinData<IIC_SSE_SQRTP_RR, [InstrStage<13, [Port0, Port1]>] >,
216 InstrItinData<IIC_SSE_SQRTP_RM, [InstrStage<14, [Port0, Port1]>] >,
217 InstrItinData<IIC_SSE_SQRTS_RR, [InstrStage<11, [Port0, Port1]>] >,
218 InstrItinData<IIC_SSE_SQRTS_RM, [InstrStage<12, [Port0, Port1]>] >,
220 InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >,
221 InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >,
226 InstrItinData<IIC_SSE_MASKMOV, [InstrStage<2, [Port0, Port1]>] >,
228 InstrItinData<IIC_SSE_PEXTRW, [InstrStage<4, [Port0, Port1]>] >,
231 InstrItinData<IIC_SSE_PABS_RR, [InstrStage<1, [Port0, Port1]>] >,
234 InstrItinData<IIC_SSE_MOV_S_RR, [InstrStage<1, [Port0, Port1]>] >,
238 InstrItinData<IIC_SSE_MOVA_P_RR, [InstrStage<1, [Port0, Port1]>] >,
242 InstrItinData<IIC_SSE_MOVU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
243 InstrItinData<IIC_SSE_MOVU_P_RM, [InstrStage<3, [Port0, Port1]>] >,
244 InstrItinData<IIC_SSE_MOVU_P_MR, [InstrStage<2, [Port0, Port1]>] >,
248 InstrItinData<IIC_SSE_LDDQU, [InstrStage<3, [Port0, Port1]>] >,
252 InstrItinData<IIC_SSE_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >,
257 InstrItinData<IIC_SSE_PAUSE, [InstrStage<17, [Port0, Port1]>] >,
258 InstrItinData<IIC_SSE_LFENCE, [InstrStage<1, [Port0, Port1]>] >,
261 InstrItinData<IIC_SSE_LDMXCSR, [InstrStage<5, [Port0, Port1]>] >,
262 InstrItinData<IIC_SSE_STMXCSR, [InstrStage<15, [Port0, Port1]>] >,
264 InstrItinData<IIC_SSE_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >,
265 InstrItinData<IIC_SSE_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >,
266 InstrItinData<IIC_SSE_PHADDSUBSW_RR, [InstrStage<7, [Port0, Port1]>] >,
267 InstrItinData<IIC_SSE_PHADDSUBSW_RM, [InstrStage<8, [Port0, Port1]>] >,
268 InstrItinData<IIC_SSE_PHADDSUBW_RR, [InstrStage<7, [Port0, Port1]>] >,
269 InstrItinData<IIC_SSE_PHADDSUBW_RM, [InstrStage<8, [Port0, Port1]>] >,
270 InstrItinData<IIC_SSE_PSHUFB_RR, [InstrStage<4, [Port0, Port1]>] >,
271 InstrItinData<IIC_SSE_PSHUFB_RM, [InstrStage<5, [Port0, Port1]>] >,
272 InstrItinData<IIC_SSE_PSIGN_RR, [InstrStage<1, [Port0, Port1]>] >,
278 InstrItinData<IIC_SSE_MWAIT, [InstrStage<46, [Port0, Port1]>] >,
279 InstrItinData<IIC_SSE_MONITOR, [InstrStage<45, [Port0, Port1]>] >,
283 InstrItinData<IIC_SSE_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >,
284 InstrItinData<IIC_SSE_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >,
286 InstrItinData<IIC_SSE_CVT_PS_RR, [InstrStage<6, [Port0, Port1]>] >,
287 InstrItinData<IIC_SSE_CVT_PS_RM, [InstrStage<7, [Port0, Port1]>] >,
288 InstrItinData<IIC_SSE_CVT_Scalar_RR, [InstrStage<6, [Port0, Port1]>] >,
289 InstrItinData<IIC_SSE_CVT_Scalar_RM, [InstrStage<7, [Port0, Port1]>] >,
290 InstrItinData<IIC_SSE_CVT_SS2SI32_RR, [InstrStage<8, [Port0, Port1]>] >,
291 InstrItinData<IIC_SSE_CVT_SS2SI32_RM, [InstrStage<9, [Port0, Port1]>] >,
292 InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<9, [Port0, Port1]>] >,
293 InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<10, [Port0, Port1]>] >,
294 InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<8, [Port0, Port1]>] >,
295 InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >,
297 InstrItinData<IIC_CMPX_LOCK, [InstrStage<14, [Port0, Port1]>] >,
298 InstrItinData<IIC_CMPX_LOCK_8, [InstrStage<6, [Port0, Port1]>] >,
299 InstrItinData<IIC_CMPX_LOCK_8B, [InstrStage<18, [Port0, Port1]>] >,
300 InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<22, [Port0, Port1]>] >,
302 InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<2, [Port0, Port1]>] >,
303 InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] >
