Lines Matching full:i16
30 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
32 ;CHECK: vclz.i16
33 %tmp1 = load <4 x i16>* %A
34 %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
35 ret <4 x i16> %tmp2
54 define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
56 ;CHECK: vclz.i16
57 %tmp1 = load <8 x i16>* %A
58 %tmp2 = call <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16> %tmp1)
59 ret <8 x i16> %tmp2
71 declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
75 declare <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16>) nounwind readnone
86 define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
89 %tmp1 = load <4 x i16>* %A
90 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
91 ret <4 x i16> %tmp2
110 define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
113 %tmp1 = load <8 x i16>* %A
114 %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
115 ret <8 x i16> %tmp2
127 declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone
131 declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) nounwind readnone
