Lines Matching full:i16
39 define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
42 %tmp1 = load <4 x i16>* %A
43 %tmp2 = load <4 x i16>* %B
44 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
45 ret <4 x i16> %tmp3
83 define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
88 %tmp1 = load <8 x i16>* %A
89 %tmp2 = load <8 x i16>* %B
90 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9>
91 ret <4 x i16> %tmp3
95 define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
98 %tmp1 = load <8 x i16>* %A
99 %tmp2 = load <8 x i16>* %B
100 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
101 ret <4 x i16> %tmp3
105 ; Use illegal <32 x i16> type to produce such a shuffle after legalizing types.
107 define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
110 %tmp1 = load <32 x i16>* %B
111 %tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <4 x i32> <i32 0, i32 8, i32 16, i32 24>
112 ret <4 x i16> %tmp2
117 define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
120 %tmp1 = load <8 x i16>* %B
121 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
122 ret <4 x i16> %tmp2
128 define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
131 %tmp1 = load <8 x i16>* %A
132 %tmp2 = load <8 x i16>* %B
133 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>
134 ret <8 x i16> %tmp3
139 define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
146 %tmp4 = trunc i32 %tmp2 to i16
147 %tmp5 = trunc i32 %tmp3 to i16
148 %tmp6 = insertelement <4 x i16> undef, i16 %tmp4, i32 0
149 %tmp7 = insertelement <4 x i16> %tmp6, i16 %tmp5, i32 1
150 store <4 x i16> %tmp7, <4 x i16>* %dest, align 4
