Lines Matching full:i16
11 define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
14 %tmp1 = load <4 x i16>* %A
15 %tmp2 = sub <4 x i16> zeroinitializer, %tmp1
16 ret <4 x i16> %tmp2
43 define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
46 %tmp1 = load <8 x i16>* %A
47 %tmp2 = sub <8 x i16> zeroinitializer, %tmp1
48 ret <8 x i16> %tmp2
75 define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
78 %tmp1 = load <4 x i16>* %A
79 %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
80 ret <4 x i16> %tmp2
99 define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
102 %tmp1 = load <8 x i16>* %A
103 %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
104 ret <8 x i16> %tmp2
116 declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) nounwind readnone
120 declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) nounwind readnone
