Lines Matching full:i16
11 define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
14 %tmp1 = load <4 x i16>* %A
15 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
16 ret <4 x i16> %tmp2
43 define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
46 %tmp1 = load <8 x i16>* %A
47 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
48 ret <8 x i16> %tmp2
75 define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
78 %tmp1 = load <4 x i16>* %A
79 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
80 ret <4 x i16> %tmp2
91 define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
94 %tmp1 = load <8 x i16>* %A
95 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
96 ret <8 x i16> %tmp2
125 define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
128 %tmp1 = load <8 x i16>* %A
129 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
130 ret <8 x i16> %tmp2
151 ; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
152 ; to <2 x i16> when stored to memory.
153 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
157 %0 = bitcast <4 x i16>* %source to <8 x i16>*
158 %tmp2 = load <8 x i16>* %0, align 4
159 %tmp3 = extractelement <8 x i16> %tmp2, i32 6
160 %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
161 %tmp9 = extractelement <8 x i16> %tmp2, i32 5
162 %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1
163 store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
