Lines Matching full:i16
10 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
17 declare <8 x i16> @llvm.spu.si.ceqh(<8 x i16>, <8 x i16>)
18 declare <4 x i32> @llvm.spu.si.ceqi(<4 x i32>, i16)
19 declare <8 x i16> @llvm.spu.si.ceqhi(<8 x i16>, i16)
24 declare <8 x i16> @llvm.spu.si.cgth(<8 x i16>, <8 x i16>)
25 declare <4 x i32> @llvm.spu.si.cgti(<4 x i32>, i16)
26 declare <8 x i16> @llvm.spu.si.cgthi(<8 x i16>, i16)
31 declare <8 x i16> @llvm.spu.si.clgth(<8 x i16>, <8 x i16>)
32 declare <4 x i32> @llvm.spu.si.clgti(<4 x i32>, i16)
33 declare <8 x i16> @llvm.spu.si.clgthi(<8 x i16>, i16)
50 define <8 x i16> @ceqhtest(<8 x i16> %A, <8 x i16> %B) {
51 call <8 x i16> @llvm.spu.si.ceqh(<8 x i16> %A, <8 x i16> %B)
52 %Y = bitcast <8 x i16> %1 to <8 x i16>
53 ret <8 x i16> %Y
63 call <4 x i32> @llvm.spu.si.ceqi(<4 x i32> %A, i16 65)
68 define <8 x i16> @ceqhitest(<8 x i16> %A) {
69 call <8 x i16> @llvm.spu.si.ceqhi(<8 x i16> %A, i16 65)
70 %Y = bitcast <8 x i16> %1 to <8 x i16>
71 ret <8 x i16> %Y
86 define <8 x i16> @cgthtest(<8 x i16> %A, <8 x i16> %B) {
87 call <8 x i16> @llvm.spu.si.cgth(<8 x i16> %A, <8 x i16> %B)
88 %Y = bitcast <8 x i16> %1 to <8 x i16>
89 ret <8 x i16> %Y
99 call <4 x i32> @llvm.spu.si.cgti(<4 x i32> %A, i16 65)
104 define <8 x i16> @cgthitest(<8 x i16> %A) {
105 call <8 x i16> @llvm.spu.si.cgthi(<8 x i16> %A, i16 65)
106 %Y = bitcast <8 x i16> %1 to <8 x i16>
107 ret <8 x i16> %Y
122 define <8 x i16> @clgthtest(<8 x i16> %A, <8 x i16> %B) {
123 call <8 x i16> @llvm.spu.si.clgth(<8 x i16> %A, <8 x i16> %B)
124 %Y = bitcast <8 x i16> %1 to <8 x i16>
125 ret <8 x i16> %Y
135 call <4 x i32> @llvm.spu.si.clgti(<4 x i32> %A, i16 65)
140 define <8 x i16> @clgthitest(<8 x i16> %A) {
141 call <8 x i16> @llvm.spu.si.clgthi(<8 x i16> %A, i16 65)
142 %Y = bitcast <8 x i16> %1 to <8 x i16>
143 ret <8 x i16> %Y
