Lines Matching full:undef
9 %tmp5.i = load volatile i32* undef ; <i32> [#uses=1]
11 %tmp12.i = load volatile i32* undef ; <i32> [#uses=1]
18 store volatile i32 %conv19.i, i32* undef
19 ret i32 undef
42 %subject19 = load %pair* undef ; <%1> [#uses=1]
44 %1 = select i1 undef, double %0, double undef ; <double> [#uses=1]
45 %2 = select i1 undef, double %1, double %0 ; <double> [#uses=1]
46 %3 = insertvalue %pair undef, double %2, 1 ; <%1> [#uses=1]
47 store %pair %3, %pair* undef
70 ret i64 undef
78 %0 = load i8* undef, align 1 ; <i8> [#uses=3]
90 store i8 %8, i8* undef, align 1
119 br i1 undef, label %bb14, label %bb67
122 %tmp0 = trunc i16 undef to i1
123 %tmp1 = load i8* undef, align 8
166 br i1 undef, label %for.inc44, label %bb.nph81
173 %l_75.077 = phi i64 [ %ins, %for.body22 ], [ undef, %bb.nph81 ]
176 %arrayidx32.0 = getelementptr [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 %tmp111, i32 0
181 %arrayidx32.1.1 = getelementptr [9 x [5 x [2 x %struct.S0]]]* undef, i32 0, i32 %l_74.0, i32 %tmp98, i32 0, i32 1, i32 %scevgep99.sum114
183 %ins = or i64 undef, undef
197 %3 = zext i96 undef to i576
199 store i576 %4, i576* undef, align 8
206 %t1 = tail call i64 @llvm.objectsize.i64(i8* undef, i1 false)
241 %tmp = load %t9** undef, align 4, !tbaa !0
247 %tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ]
248 %tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ]
249 br i1 undef, label %bb34, label %bb7
252 %tmp8 = load i32* undef, align 4
258 %tmp14 = load i32* undef, align 4
264 %tmp20 = load i8* undef, align 1
269 store i96 %tmp24, i96* undef, align 4
271 %tmp26 = icmp eq %t13* %tmp25, undef
278 call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef)
282 store i96 %tmp23, i96* undef, align 4
295 br i1 undef, label %bb36, label %bb35
302 call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef)
308 %tmp40 = add i32 undef, 1
321 ; Spilling a virtual register with <undef> uses.
324 %Shuff = shufflevector <8 x double> undef, <8 x double> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 undef>
330 br i1 undef, label %CF, label %CF75
333 br i1 undef, label %CF75, label %CF76
336 store double %E19, double* undef
337 br i1 undef, label %CF76, label %CF77
340 %B55 = fmul <8 x double> %B16, undef
353 %3 = or <2 x i32> undef, %2
354 %4 = and <2 x i32> %3, undef
355 store <2 x i32> %4, <2 x i32>* undef
356 %5 = load <2 x i32>* undef, align 1
361 %7 = icmp ult i32 undef, undef
