Lines Matching defs:RC
130 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
133 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
134 const CodeGenRegister::Set &Regs = RC.getMembers();
139 RC.buildRegUnitSet(RegUnits);
143 OS << "}, \t// " << RC.getName() << "\n";
146 << " return RCWeightTable[RC->getID()];\n"
172 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"
192 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
535 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
536 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
537 ArrayRef<Record*> Order = RC.getOrder();
540 std::string Name = RC.getName();
569 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
570 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
574 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
575 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
576 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
578 OS << " { " << '\"' << RC.getName() << "\", "
579 << RC.getName() << ", " << RC.getName() << "Bits, "
580 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
581 << RC.getQualifiedName() + "RegClassID" << ", "
582 << RC.SpillSize/8 << ", "
583 << RC.SpillAlignment/8 << ", "
584 << RC.CopyCost << ", "
585 << RC.Allocatable << " },\n";
672 << "const TargetRegisterClass *RC) const;\n"
676 << "const TargetRegisterClass *RC) const;\n"
686 const CodeGenRegisterClass &RC = *RegisterClasses[i];
687 const std::string &Name = RC.getName();
725 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
726 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
727 ArrayRef<Record*> Order = RC.getOrder();
729 if (RC.Allocatable)
735 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
736 VTSeqs.add(RegisterClasses[rc]->VTs);
753 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
754 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
756 i = RC.SubRegClasses.begin(),
757 e = RC.SubRegClasses.end(); i != e; ++i) {
761 SuperRegClassMap[RC2->EnumValue].insert(rc);
766 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
767 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
770 std::string Name = RC.getName();
779 SuperRegClassMap.find(rc);
797 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
798 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
801 std::string Name = RC.getName();
804 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
809 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
810 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
811 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
818 << RC.getName() << "Superclasses[] = {\n";
826 const CodeGenRegisterClass &RC = *RegisterClasses[i];
827 if (!RC.AltOrderSelect.empty()) {
828 OS << "\nstatic inline unsigned " << RC.getName()
830 << RC.AltOrderSelect << "}\n\n"
831 << "static ArrayRef<uint16_t> " << RC.getName()
833 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
834 ArrayRef<Record*> Elems = RC.getOrder(oi);
843 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
846 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
847 if (RC.getOrder(oi).empty())
851 OS << ")\n };\n const unsigned Select = " << RC.getName()
852 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
862 const CodeGenRegisterClass &RC = *RegisterClasses[i];
865 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
867 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
868 << RC.getName() << "SubclassMask,\n ";
869 if (RC.getSuperClasses().empty())
872 OS << RC.getName() << "Superclasses,\n ";
873 OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
875 if (RC.AltOrderSelect.empty())
878 OS << RC.getName() << "GetRawAllocationOrder\n";
964 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
968 << " return RC;\n";
980 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
981 OS << " {\t// " << RC.getName() << "\n";
984 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
992 OS << " };\n assert(RC && \"Missing regclass\");\n"
993 << " if (!Idx) return RC;\n --Idx;\n"
995 << " unsigned TV = Table[RC->getID()][Idx];\n"
1021 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1022 OS << " {\t// " << RC.getName() << "\n";
1026 RC.getSuperRegClasses(Idx, BV);
