Lines Matching refs:irq_state
172 if (s->gic.irq_state[irq].pending) {
178 if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
181 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
184 if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
207 if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
208 if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
209 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
210 if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
211 if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
212 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
213 if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
214 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
215 if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
216 if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
217 if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
218 if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
219 if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
220 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
310 s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
316 s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
351 s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
352 s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
353 s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
