Lines Matching refs:OP
189 i |= (op & o->bitm) << o->shift;
191 this structure, and op is the operand value).
201 (unsigned long instruction, long op, int dialect, const char **errmsg);
207 op = (i >> o->shift) & o->bitm;
209 sign_extend (op);
210 (i is the instruction, o is a pointer to this structure, and op
245 insert function with any op value. The disassembler should call
1597 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1598 #define OP_MASK OP (0x3f)
1603 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1609 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1613 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1629 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1633 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1647 #define BBOCB(op, bo, cb, aa, lk) \
1648 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1661 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1665 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1672 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1676 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1680 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1684 #define M(op, rc) (OP (op) | ((rc) & 1))
1688 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1697 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1707 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1714 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1718 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1724 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1730 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1736 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1739 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1742 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1745 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1782 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1792 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1796 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1800 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1809 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1813 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1817 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1821 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1824 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1830 #define XLO(op, bo, xop, lk) \
1831 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1836 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1841 #define XLOCB(op, bo, cb, xop, lk) \
1842 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1860 #define XO(op, xop, oe, rc) \
1861 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1868 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1875 #define XFXM(op, xop, fxm, p4) \
1876 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1880 #define XSPR(op, xop, spr) \
1881 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1896 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2030 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2588 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2589 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2591 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2592 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2594 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2603 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2604 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2608 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2609 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2611 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2612 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2613 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2615 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2616 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2617 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2619 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2620 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2621 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2622 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2623 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2624 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2626 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2627 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2628 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2629 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2630 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
3356 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3357 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3358 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3360 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3361 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3363 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3364 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3366 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3367 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3369 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3370 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3372 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3373 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
4628 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4629 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4631 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4632 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4634 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4636 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4638 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4639 OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4641 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4642 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4644 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4646 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4648 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4650 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4652 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4654 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4656 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4658 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4660 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4661 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4663 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4664 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4666 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4668 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4670 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4672 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4674 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4676 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4678 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4680 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4682 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4684 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4686 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4688 { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4811 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4813 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4815 { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
5260 unsigned long op;
5278 op = PPC_OP (insn);
5295 if (op < table_op)
5297 if (op > table_op)
