Home | History | Annotate | Download | only in target-arm

Lines Matching defs:rm

855     int val, rm, shift, shiftop;
867 rm = (insn) & 0xf;
870 offset = load_reg(s, rm);
883 int val, rm;
898 rm = (insn) & 0xf;
899 offset = load_reg(s, rm);
2727 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2965 rm = VFP_SREG_M(insn);
2967 VFP_DREG_M(rm, insn);
2980 rm = VFP_SREG_M(insn);
3008 if ((rm & bank_mask) == 0) {
3024 gen_mov_F0_vreg(0, rm);
3030 gen_mov_F1_vreg(dp, rm);
3051 gen_mov_F0_vreg(dp, rm);
3057 gen_mov_F1_vreg(dp, rm);
3213 gen_vfp_shto(dp, 16 - rm, 0);
3218 gen_vfp_slto(dp, 32 - rm, 0);
3223 gen_vfp_uhto(dp, 16 - rm, 0);
3228 gen_vfp_ulto(dp, 32 - rm, 0);
3245 gen_vfp_tosh(dp, 16 - rm, 0);
3250 gen_vfp_tosl(dp, 32 - rm, 0);
3255 gen_vfp_touh(dp, 16 - rm, 0);
3260 gen_vfp_toul(dp, 32 - rm, 0);
3304 rm = ((rm + delta_m) & (bank_mask - 1))
3305 | (rm & bank_mask);
3306 gen_mov_F0_vreg(dp, rm);
3313 rm = ((rm + delta_m) & (bank_mask - 1))
3314 | (rm & bank_mask);
3315 gen_mov_F1_vreg(dp, rm);
3328 VFP_DREG_M(rm, insn);
3330 rm = VFP_SREG_M(insn);
3336 gen_mov_F0_vreg(0, rm * 2);
3339 gen_mov_F0_vreg(0, rm * 2 + 1);
3343 gen_mov_F0_vreg(0, rm);
3346 gen_mov_F0_vreg(0, rm + 1);
3355 gen_mov_vreg_F0(0, rm * 2);
3358 gen_mov_vreg_F0(0, rm * 2 + 1);
3362 gen_mov_vreg_F0(0, rm);
3365 gen_mov_vreg_F0(0, rm + 1);
3687 static int gen_neon_unzip(int rd, int rm, int size, int q)
3694 tmp2 = tcg_const_i32(rm);
3726 static int gen_neon_zip(int rd, int rm, int size, int q)
3733 tmp2 = tcg_const_i32(rm);
3829 int rd, rn, rm;
3848 rm = insn & 0xf;
4031 if (rm != 15) {
4035 if (rm == 13) {
4039 index = load_reg(s, rm);
4420 int rd, rn, rm;
4437 VFP_DREG_M(rm, insn);
4449 if (q && ((rd | rn | rm) & 1)) {
4456 neon_load_reg64(cpu_V1, rm + pass);
4524 rn = rm;
4525 rm = rtmp;
4582 tmp = neon_load_reg(rm, 0);
4583 tmp2 = neon_load_reg(rm, 1);
4588 tmp2 = neon_load_reg(rm, pass);
4824 if (pairwise && rd == rm) {
4831 if (pairwise && rd == rm) {
4859 if (q && ((rd | rm) & 1)) {
4894 neon_load_reg64(cpu_V0, rm + pass);
4951 tmp = neon_load_reg(rm, pass);
5041 if (rm & 1) {
5048 neon_load_reg64(cpu_V0, rm);
5049 neon_load_reg64(cpu_V1, rm + 1);
5084 tmp4 = neon_load_reg(rm + 1, 0);
5085 tmp5 = neon_load_reg(rm + 1, 1);
5088 tmp = neon_load_reg(rm, 0);
5095 tmp3 = neon_load_reg(rm, 1);
5115 tmp = neon_load_reg(rm, 0);
5116 tmp2 = neon_load_reg(rm, 1);
5155 if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
5163 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
5309 (src2_wide && (rm & 1)) ||
5317 if (rd == rm && !src2_wide) {
5318 tmp = neon_load_reg(rm, 1);
5340 neon_load_reg64(cpu_V1, rm + pass);
5343 if (pass == 1 && rd == rm) {
5346 tmp2 = neon_load_reg(rm, pass);
5489 tmp = neon_get_scalar(size, rm);
5554 tmp2 = neon_get_scalar(size, rm);
5612 if (q && ((rd | rn | rm) & 1)) {
5624 neon_load_reg64(cpu_V1, rm);
5633 neon_load_reg64(tmp64, rm);
5639 neon_load_reg64(cpu_V1, rm);
5641 neon_load_reg64(cpu_V1, rm + 1);
5652 neon_load_reg64(cpu_V1, rm);
5669 q && ((rm | rd) & 1)) {
5675 tmp = neon_load_reg(rm, pass * 2);
5676 tmp2 = neon_load_reg(rm, pass * 2 + 1);
5699 tmp = neon_load_reg(rm, pass * 2);
5701 tmp = neon_load_reg(rm, pass * 2 + 1);
5721 tmp = neon_load_reg(rm, n);
5723 neon_store_reg(rm, n, tmp2);
5731 if (gen_neon_unzip(rd, rm, size, q)) {
5736 if (gen_neon_zip(rd, rm, size, q)) {
5742 if (rm & 1) {
5747 neon_load_reg64(cpu_V0, rm + pass);
5763 tmp = neon_load_reg(rm, 0);
5764 tmp2 = neon_load_reg(rm, 1);
5775 q || (rm & 1)) {
5780 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5782 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5786 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5788 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5803 tmp = neon_load_reg(rm, 0);
5804 tmp2 = neon_load_reg(rm, 1);
5826 neon_reg_offset(rm, pass));
5829 tmp = neon_load_reg(rm, pass);
5962 neon_store_reg(rm, pass, tmp2);
5971 neon_store_reg(rm, pass, tmp2);
6028 tmp2 = neon_load_reg(rm, 0);
6039 tmp3 = neon_load_reg(rm, 1);
6052 tmp = neon_load_reg(rm, 1);
6054 tmp = neon_load_reg(rm, 0);
6417 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6702 rm = insn & 0xf;
6707 tmp = load_reg(s, rm);
6729 tmp = load_reg(s, rm);
6735 tmp = load_reg(s, rm);
6746 tmp = load_reg(s, rm);
6758 tmp = load_reg(s, rm);
6768 tmp = load_reg(s, rm);
6804 tmp = load_reg(s, rm);
6823 tmp = load_reg(s, rm);
6871 rm = (insn) & 0xf;
6872 tmp2 = load_reg(s, rm);
7041 rm = (insn) & 0xf;
7047 tmp2 = load_reg(s, rm);
7070 tmp2 = load_reg(s, rm);
7081 tmp2 = load_reg(s, rm);
7129 rm = insn & 0xf;
7132 gen_store_exclusive(s, rd, rm, 15, addr, 2);
7135 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
7138 gen_store_exclusive(s, rd, rm, 15, addr, 0);
7141 gen_store_exclusive(s, rd, rm, 15, addr, 1);
7150 rm = (insn) & 0xf;
7156 tmp = load_reg(s, rm);
7248 rm = insn & 0xf;
7256 tmp2 = load_reg(s, rm);
7268 tmp2 = load_reg(s, rm);
7289 tmp = load_reg(s, rm);
7308 tmp = load_reg(s, rm);
7320 tmp2 = load_reg(s, rm);
7328 tmp = load_reg(s, rm);
7356 tmp = load_reg(s, rm);
7376 tmp = load_reg(s, rm);
7439 tmp = load_reg(s, rm);
7456 if (rm == 15) {
7460 tmp = load_reg(s, rm);
7472 tmp = load_reg(s, rm);
7782 uint32_t rd, rn, rm, rs;
7847 rm = insn & 0xf;
7913 tmp = load_reg(s, rm);
7940 gen_store_exclusive(s, rm, rs, rd, addr, op);
8062 tmp2 = load_reg(s, rm);
8089 tmp2 = load_reg(s, rm);
8113 tmp2 = load_reg(s, rm);
8124 tmp = load_reg(s, rm);
8157 tmp2 = load_reg(s, rm);
8167 tmp2 = load_reg(s, rm);
8191 tmp2 = load_reg(s, rm);
8210 tmp2 = load_reg(s, rm);
8306 tmp2 = load_reg(s, rm);
8771 tmp = load_reg(s, rm);
8852 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8891 rm = (insn >> 6) & 7;
8892 tmp2 = load_reg(s, rm);
8909 rm = (insn >> 3) & 7;
8911 tmp = load_reg(s, rm);
8973 rm = (insn >> 3) & 0xf;
8978 tmp2 = load_reg(s, rm);
8985 tmp2 = load_reg(s, rm);
8991 tmp = load_reg(s, rm);
8995 tmp = load_reg(s, rm);
9012 rm = (insn >> 3) & 7;
9016 val = rm;
9017 rm = rd;
9033 tmp2 = load_reg(s, rm);
9129 rm = rd;
9134 store_reg(s, rm, tmp2);
9151 rm = (insn >> 6) & 7;
9154 tmp = load_reg(s, rm);
9304 rm = (insn >> 3) & 7;
9305 tmp = load_reg(s, rm);
9371 rm = insn & 7;
9372 tmp = load_reg(s, rm);