Lines Matching defs:shift
258 static void gen_ubfx(TCGv var, int shift, uint32_t mask)
260 if (shift)
261 tcg_gen_shri_i32(var, var, shift);
266 static void gen_sbfx(TCGv var, int shift, int width)
270 if (shift)
271 tcg_gen_sari_i32(var, var, shift);
272 if (shift + width < 32) {
281 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
284 tcg_gen_shli_i32(val, val, shift);
285 tcg_gen_andi_i32(base, base, ~(mask << shift));
430 static void shifter_out_im(TCGv var, int shift)
433 if (shift == 0) {
436 tcg_gen_shri_i32(tmp, var, shift);
437 if (shift != 31)
444 /* Shift by immediate. Includes special handling for shift == 0. */
445 static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
449 if (shift != 0) {
451 shifter_out_im(var, 32 - shift);
452 tcg_gen_shli_i32(var, var, shift);
456 if (shift == 0) {
464 shifter_out_im(var, shift - 1);
465 tcg_gen_shri_i32(var, var, shift);
469 if (shift == 0)
470 shift = 32;
472 shifter_out_im(var, shift - 1);
473 if (shift == 32)
474 shift = 31;
475 tcg_gen_sari_i32(var, var, shift);
478 if (shift != 0) {
480 shifter_out_im(var, shift - 1);
481 tcg_gen_rotri_i32(var, var, shift); break;
495 TCGv shift, int flags)
499 case 0: gen_helper_shl_cc(var, var, shift); break;
500 case 1: gen_helper_shr_cc(var, var, shift); break;
501 case 2: gen_helper_sar_cc(var, var, shift); break;
502 case 3: gen_helper_ror_cc(var, var, shift); break;
506 case 0: gen_helper_shl(var, var, shift); break;
507 case 1: gen_helper_shr(var, var, shift); break;
508 case 2: gen_helper_sar(var, var, shift); break;
509 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
510 tcg_gen_rotr_i32(var, var, shift); break;
513 tcg_temp_free_i32(shift);
855 int val, rm, shift, shiftop;
866 /* shift/register */
868 shift = (insn >> 7) & 0x1f;
871 gen_arm_shift_im(offset, shiftop, shift, 0);
1041 static inline void gen_vfp_##name(int dp, int shift, int neon) \
1043 TCGv tmp_shift = tcg_const_i32(shift); \
2670 static void gen_neon_dup_u8(TCGv var, int shift)
2673 if (shift)
2674 tcg_gen_shri_i32(var, var, shift);
3839 int shift;
3937 shift = ((insn >> 5) & 3) * 8;
3941 shift = ((insn >> 6) & 1) * 16;
3945 shift = 0;
4004 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
4010 if (shift)
4011 tcg_gen_shri_i32(tmp, tmp, shift);
4096 static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4102 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4103 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4108 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4109 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4116 case 1: gen_helper_neon_shl_u16(var, var, shift); break;
4117 case 2: gen_helper_neon_shl_u32(var, var, shift); break;
4122 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4123 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4422 int shift;
4522 /* Shift instruction operands are reversed. */
4840 /* Two registers and shift. */
4843 /* 64-bit shift. */
4853 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4854 /* To avoid excessive dumplication of ops we implement shift
4855 by immediate using the variable shift operations. */
4857 /* Shift by immediate:
4865 /* Right shifts are encoded as N - shift, where N is the
4868 shift = shift - (1 << (size + 3));
4876 imm = (uint8_t) shift;
4881 imm = (uint16_t) shift;
4886 imm = shift;
4936 if (shift < -63 || shift > 63) {
4940 mask = 0xffffffffffffffffull >> -shift;
4942 mask = 0xffffffffffffffffull << shift;
5002 mask = 0xff >> -shift;
5004 mask = (uint8_t)(0xff << shift);
5010 mask = 0xffff >> -shift;
5012 mask = (uint16_t)(0xffff << shift);
5016 if (shift < -31 || shift > 31) {
5020 mask = 0xffffffffu >> -shift;
5022 mask = 0xffffffffu << shift;
5038 /* Shift by immediate and narrow:
5044 shift = shift - (1 << (size + 3));
5047 tmp64 = tcg_const_i64(shift);
5077 imm = (uint16_t)shift;
5081 imm = (uint32_t)shift;
5123 if (shift != 0) {
5124 /* The shift is less than the width of the source
5125 type, so we can just shift the whole register. */
5126 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
5127 /* Widen the result of shift: we need to clear
5135 imm = (0xffu >> (8 - shift));
5138 imm = 0xffff >> (16 - shift);
5141 imm = 0xffffffff >> (32 - shift);
5159 * hence this 32-shift where the ARM ARM has 64-imm6.
5161 shift = 32 - shift;
5166 gen_vfp_ulto(0, shift, 1);
5168 gen_vfp_slto(0, shift, 1);
5171 gen_vfp_toul(0, shift, 1);
5173 gen_vfp_tosl(0, shift, 1);
6417 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6689 shift = ((insn >> 8) & 0xf) * 2;
6690 if (shift)
6691 val = (val >> shift) | (val << (32 - shift));
6860 shift = ((insn >> 8) & 0xf) * 2;
6861 if (shift) {
6862 val = (val >> shift) | (val << (32 - shift));
6866 if (logic_cc && shift) {
6875 shift = (insn >> 7) & 0x1f;
6876 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7269 shift = (insn >> 7) & 0x1f;
7272 if (shift == 0)
7273 shift = 31;
7274 tcg_gen_sari_i32(tmp2, tmp2, shift);
7279 if (shift)
7280 tcg_gen_shli_i32(tmp2, tmp2, shift);
7290 shift = (insn >> 7) & 0x1f;
7292 if (shift == 0)
7293 shift = 31;
7294 tcg_gen_sari_i32(tmp, tmp, shift);
7296 tcg_gen_shli_i32(tmp, tmp, shift);
7329 shift = (insn >> 10) & 3;
7331 rotate, a shift is sufficient. */
7332 if (shift != 0)
7333 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
7453 shift = (insn >> 7) & 0x1f;
7455 i = i + 1 - shift;
7464 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
7473 shift = (insn >> 7) & 0x1f;
7475 if (shift + i > 32)
7479 gen_ubfx(tmp, shift, (1u << i) - 1);
7481 gen_sbfx(tmp, shift, i);
7781 uint32_t insn, imm, shift, offset;
8063 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
8066 if (shift == 0)
8067 shift = 31;
8068 tcg_gen_sari_i32(tmp2, tmp2, shift);
8073 if (shift)
8074 tcg_gen_shli_i32(tmp2, tmp2, shift);
8082 /* Data processing register constant shift. */
8092 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
8095 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
8111 case 0: /* Register controlled shift. */
8125 shift = (insn >> 4) & 3;
8127 rotate, a shift is sufficient. */
8128 if (shift != 0)
8129 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
8153 shift = (insn >> 4) & 7;
8154 if ((op & 3) == 3 || (shift & 3) == 3)
8158 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
8554 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
8564 if (shift + imm > 32)
8567 gen_sbfx(tmp, shift, imm);
8571 if (shift + imm > 32)
8574 gen_ubfx(tmp, shift, (1u << imm) - 1);
8577 if (imm < shift)
8579 imm = imm + 1 - shift;
8582 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
8589 if (shift) {
8591 tcg_gen_sari_i32(tmp, tmp, shift);
8593 tcg_gen_shli_i32(tmp, tmp, shift);
8598 if ((op & 1) && shift == 0)
8604 if ((op & 1) && shift == 0)
8652 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8654 switch (shift) {
8670 shift = (shift << 1) | (imm >> 7);
8672 imm = imm << (32 - shift);
8766 shift = (insn >> 4) & 0xf;
8767 if (shift > 3) {
8772 if (shift)
8773 tcg_gen_shli_i32(tmp, tmp, shift);
8852 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8908 /* shift immediate */
8910 shift = (insn >> 6) & 0x1f;
8912 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
9015 /* the shift/rotate ops want the operands backwards */
9438 shift = CPSR_A | CPSR_I | CPSR_F;
9440 shift = 0;
9441 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
