Lines Matching refs:rn
1187 rn)
1189 iwmmxt_store_reg(cpu_M0, rn);
1192 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1194 iwmmxt_load_reg(cpu_M0, rn);
1197 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1199 iwmmxt_load_reg(cpu_V1, rn);
1203 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1205 iwmmxt_load_reg(cpu_V1, rn);
1209 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1211 iwmmxt_load_reg(cpu_V1, rn);
1216 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1218 iwmmxt_load_reg(cpu_V1, rn); \
1313 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1315 iwmmxt_load_reg(cpu_V1, rn);
2727 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2740 rn = (insn >> 16) & 0xf;
2741 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2742 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
2755 VFP_DREG_N(rn, insn);
2775 tmp = neon_load_reg(rn, pass);
2817 neon_store_reg(rn, n, tmp2);
2819 neon_store_reg(rn, n, tmp);
2824 tmp2 = neon_load_reg(rn, pass);
2829 tmp2 = neon_load_reg(rn, pass);
2836 neon_store_reg(rn, pass, tmp);
2842 rn = VFP_SREG_N(insn);
2847 rn >>= 1;
2849 switch (rn) {
2857 tmp = load_cpu_field(vfp.xregs[rn]);
2862 tmp = load_cpu_field(vfp.xregs[rn]);
2870 tmp = load_cpu_field(vfp.xregs[rn]);
2886 tmp = load_cpu_field(vfp.xregs[rn]);
2892 gen_mov_F0_vreg(0, rn);
2906 rn >>= 1;
2908 switch (rn) {
2925 store_cpu_field(tmp, vfp.xregs[rn]);
2930 store_cpu_field(tmp, vfp.xregs[rn]);
2937 gen_mov_vreg_F0(0, rn);
2947 /* rn is opcode */
2948 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2950 /* rn is register number */
2951 VFP_DREG_N(rn, insn);
2954 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
2961 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2970 rn = VFP_SREG_N(insn);
2971 if (op == 15 && rn == 15) {
2984 if (op == 15 && rn > 3)
3020 switch (rn) {
3056 gen_mov_F0_vreg(dp, rn);
3131 switch (rn) {
3263 printf ("rn:%d\n", rn);
3273 if (op == 15 && (rn >= 8 && rn <= 11))
3275 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3278 else if (op == 15 && rn == 15)
3309 rn = ((rn + delta_d) & (bank_mask - 1))
3310 | (rn & bank_mask);
3311 gen_mov_F0_vreg(dp, rn);
3325 rn = (insn >> 16) & 0xf;
3341 store_reg(s, rn, tmp);
3348 store_reg(s, rn, tmp);
3356 tmp = load_reg(s, rn);
3363 tmp = load_reg(s, rn);
3370 rn = (insn >> 16) & 0xf;
3375 if (s->thumb && rn == 15) {
3379 addr = load_reg(s, rn);
3434 store_reg(s, rn, addr);
3829 int rd, rn, rm;
3847 rn = (insn >> 16) & 0xf;
3906 load_reg_var(s, addr, rn);
3986 load_reg_var(s, addr, rn);
4034 base = load_reg(s, rn);
4043 store_reg(s, rn, base);
4420 int rd, rn, rm;
4436 VFP_DREG_N(rn, insn);
4449 if (q && ((rd | rn | rm) & 1)) {
4455 neon_load_reg64(cpu_V0, rn + pass);
4523 rtmp = rn;
4524 rn = rm;
4579 tmp = neon_load_reg(rn, 0);
4580 tmp2 = neon_load_reg(rn, 1);
4587 tmp = neon_load_reg(rn, pass);
5308 if ((src1_wide && (rn & 1)) ||
5320 } else if (rd == rn && !src1_wide) {
5321 tmp = neon_load_reg(rn, 1);
5327 neon_load_reg64(cpu_V0, rn + pass);
5330 if (pass == 1 && rd == rn) {
5333 tmp = neon_load_reg(rn, pass);
5486 if (u && ((rd | rn) & 1)) {
5493 tmp2 = neon_load_reg(rn, pass);
5559 tmp3 = neon_load_reg(rn, 1);
5563 tmp = neon_load_reg(rn, 0);
5612 if (q && ((rd | rn | rm) & 1)) {
5617 neon_load_reg64(cpu_V0, rn);
5619 neon_load_reg64(cpu_V1, rn + 1);
5622 neon_load_reg64(cpu_V0, rn + 1);
5629 neon_load_reg64(cpu_V0, rn);
5630 neon_load_reg64(tmp64, rn + 1);
5632 neon_load_reg64(cpu_V0, rn + 1);
5650 neon_load_reg64(cpu_V0, rn);
6015 if ((rn + n) > 32) {
6029 tmp4 = tcg_const_i32(rn);
6270 /* Load 64-bit value rd:rn. */
6417 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6563 rn = (insn >> 16) & 0xf;
6564 addr = load_reg(s, rn);
6590 store_reg(s, rn, addr);
6767 rn = (insn >> 16) & 0xf;
6769 tmp2 = load_reg(s, rn);
6800 rn = (insn >> 12) & 0xf;
6816 tmp2 = load_reg(s, rn);
6831 gen_addq(s, tmp64, rn, rd);
6832 gen_storeq_reg(s, rn, rd, tmp64);
6836 tmp2 = load_reg(s, rn);
6884 rn = (insn >> 16) & 0xf;
6885 tmp = load_reg(s, rn);
7039 rn = (insn >> 12) & 0xf;
7053 tmp2 = load_reg(s, rn);
7058 tmp2 = load_reg(s, rn);
7072 gen_addq_lo(s, tmp64, rn);
7074 gen_storeq_reg(s, rn, rd, tmp64);
7088 gen_addq(s, tmp64, rn, rd);
7093 gen_storeq_reg(s, rn, rd, tmp64);
7100 rn = (insn >> 16) & 0xf;
7110 load_reg_var(s, addr, rn);
7155 addr = load_reg(s, rn);
7172 rn = (insn >> 16) & 0xf;
7174 addr = load_reg(s, rn);
7226 store_reg(s, rn, addr);
7230 store_reg(s, rn, addr);
7249 rn = (insn >> 16) & 0xf;
7255 tmp = load_reg(s, rn);
7267 tmp = load_reg(s, rn);
7319 tmp = load_reg(s, rn);
7344 if (rn != 15) {
7345 tmp2 = load_reg(s, rn);
7398 store_reg(s, rn, tmp);
7419 gen_addq(s, tmp64, rd, rn);
7420 gen_storeq_reg(s, rd, rn, tmp64);
7430 store_reg(s, rn, tmp);
7448 store_reg(s, rn, tmp);
7504 rn = (insn >> 16) & 0xf;
7506 tmp2 = load_reg(s, rn);
7527 store_reg(s, rn, tmp2);
7529 store_reg(s, rn, tmp2);
7553 rn = (insn >> 16) & 0xf;
7554 addr = load_reg(s, rn);
7594 } else if (i == rn) {
7642 store_reg(s, rn, addr);
7648 store_reg(s, rn, loaded_var);
7782 uint32_t rd, rn, rm, rs;
7844 rn = (insn >> 16) & 0xf;
7857 if (rn == 15) {
7861 addr = load_reg(s, rn);
7887 if (rn == 15)
7890 store_reg(s, rn, addr);
7897 load_reg_var(s, addr, rn);
7907 if (rn == 15) {
7911 addr = load_reg(s, rn);
7936 load_reg_var(s, addr, rn);
7952 addr = load_reg(s, rn);
7966 store_reg(s, rn, addr);
8004 addr = load_reg(s, rn);
8024 } else if (i == rn) {
8038 store_reg(s, rn, loaded_var);
8047 if (insn & (1 << rn))
8049 store_reg(s, rn, addr);
8061 tmp = load_reg(s, rn);
8083 rn == 15) {
8087 tmp = load_reg(s, rn);
8112 tmp = load_reg(s, rn);
8140 if (rn != 15) {
8141 tmp2 = load_reg(s, rn);
8156 tmp = load_reg(s, rn);
8166 tmp = load_reg(s, rn);
8176 tmp = load_reg(s, rn);
8209 tmp = load_reg(s, rn);
8305 tmp = load_reg(s, rn);
8426 tmp = load_reg(s, rn);
8438 tmp = load_reg(s, rn);
8489 tmp = load_reg(s, rn);
8496 if (rn != 14 || rd != 15) {
8499 tmp = load_reg(s, rn);
8555 if (rn == 15) {
8559 tmp = load_reg(s, rn);
8631 if (rn == 15) {
8640 tmp = load_reg(s, rn);
8678 rn = (insn >> 16) & 0xf;
8679 if (rn == 15) {
8683 tmp = load_reg(s, rn);
8731 if (rn == 15) {
8746 if (rn == 15) {
8757 addr = load_reg(s, rn);
8836 store_reg(s, rn, addr);
8852 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8883 rn = (insn >> 3) & 7;
8884 tmp = load_reg(s, rn);
9150 rn = (insn >> 3) & 7;
9153 addr = load_reg(s, rn);
9195 rn = (insn >> 3) & 7;
9196 addr = load_reg(s, rn);
9215 rn = (insn >> 3) & 7;
9216 addr = load_reg(s, rn);
9235 rn = (insn >> 3) & 7;
9236 addr = load_reg(s, rn);
9404 rn = (insn >> 3) & 0x7;
9406 tmp = load_reg(s, rn);
9455 rn = (insn >> 8) & 0x7;
9456 addr = load_reg(s, rn);
9462 if (i == rn) {
9476 if ((insn & (1 << rn)) == 0) {
9478 store_reg(s, rn, addr);
9482 store_reg(s, rn, loaded_var);
