Lines Matching refs:vfp
998 offset = offsetof(CPUState, vfp.standard_fp_status); \
1000 offset = offsetof(CPUState, vfp.fp_status); \
1021 offset = offsetof(CPUState, vfp.standard_fp_status); \
1023 offset = offsetof(CPUState, vfp.fp_status); \
1047 offset = offsetof(CPUState, vfp.standard_fp_status); \
1049 offset = offsetof(CPUState, vfp.fp_status); \
1090 return offsetof(CPUARMState, vfp.regs[reg]);
1092 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1095 return offsetof(CPUARMState, vfp.regs[reg >> 1])
2656 /* Move between integer and VFP cores. */
2723 /* Disassemble a VFP instruction. Returns nonzero if an error occurred
2737 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2774 /* vfp->arm */
2805 /* arm->vfp */
2844 /* vfp->arm */
2857 tmp = load_cpu_field(vfp.xregs[rn]);
2862 tmp = load_cpu_field(vfp.xregs[rn]);
2870 tmp = load_cpu_field(vfp.xregs[rn]);
2874 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2886 tmp = load_cpu_field(vfp.xregs[rn]);
2903 /* arm->vfp */
2922 /* TODO: VFP subarchitecture support.
2925 store_cpu_field(tmp, vfp.xregs[rn]);
2930 store_cpu_field(tmp, vfp.xregs[rn]);
3334 /* vfp->arm */
3351 /* arm->vfp */
3661 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3667 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
9881 d.d = env->vfp.regs[i];
9891 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
