Lines Matching defs:shift
136 /* i386 shift ops */
462 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
465 if (shift != 0)
466 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
504 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
507 if (shift != 0)
508 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
1467 /* update eflags if non zero shift */
1535 /* update eflags if non zero shift */
1681 int shift = op2 & ((1 << (3 + ot)) - 1);
1683 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1684 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1687 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1688 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1817 /* Note: we implement the Intel behaviour for shift count > 16 */
3428 case 0x71: /* shift mm, im */
3431 case 0x171: /* shift xmm, im */
4044 int shift, ot;
5336 /* shift Ev,Ib */
5337 shift = 2;
5350 if (shift == 2) {
5360 if (shift == 0) {
5363 if (shift == 2) {
5364 shift = ldub_code(s->pc++);
5366 gen_shifti(s, op, ot, opreg, shift);
5372 /* shift Ev,1 */
5373 shift = 1;
5377 /* shift Ev,cl */
5378 shift = 0;
5383 shift = 1;
5387 shift = 0;
5391 shift = 1;
5395 shift = 0;
5410 if (shift) {
6458 /* load shift */
