Lines Matching refs:reg
274 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
278 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
279 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
281 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
285 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
289 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
292 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
296 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
301 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
307 static inline void gen_op_mov_reg_T0(int ot, int reg)
309 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
312 static inline void gen_op_mov_reg_T1(int ot, int reg)
314 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
317 static inline void gen_op_mov_reg_A0(int size, int reg)
321 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
325 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
328 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
332 tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
337 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
343 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
347 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
350 tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
355 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
360 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
362 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
365 static inline void gen_op_movl_A0_reg(int reg)
367 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
405 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
409 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
411 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
414 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
419 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
423 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
425 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
431 static inline void gen_op_add_reg_T0(int size, int reg)
435 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
437 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
440 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
445 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
449 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
451 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
462 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
464 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
473 static inline void gen_op_movl_A0_seg(int reg)
475 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
478 static inline void gen_op_addl_A0_seg(int reg)
480 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
488 static inline void gen_op_movq_A0_seg(int reg)
490 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
493 static inline void gen_op_addq_A0_seg(int reg)
495 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
499 static inline void gen_op_movq_A0_reg(int reg)
501 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
504 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
506 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
670 static void gen_extu(int ot, TCGv reg)
674 tcg_gen_ext8u_tl(reg, reg);
677 tcg_gen_ext16u_tl(reg, reg);
680 tcg_gen_ext32u_tl(reg, reg);
687 static void gen_exts(int ot, TCGv reg)
691 tcg_gen_ext8s_tl(reg, reg);
694 tcg_gen_ext16s_tl(reg, reg);
697 tcg_gen_ext32s_tl(reg, reg);
821 /* compute eflags.C to reg */
822 static void gen_compute_eflags_c(TCGv reg)
825 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
829 static void gen_compute_eflags(TCGv reg)
832 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
2223 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2225 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2233 if (reg != OR_TMP0)
2234 gen_op_mov_TN_reg(ot, 0, reg);
2238 if (reg != OR_TMP0)
2239 gen_op_mov_reg_T0(ot, reg);
2244 if (reg != OR_TMP0)
2245 gen_op_mov_TN_reg(ot, 0, reg);
2249 if (reg != OR_TMP0)
2250 gen_op_mov_reg_T0(ot, reg);
3091 int modrm, mod, rm, reg, reg_addr, offset_addr;
3148 reg = ((modrm >> 3) & 7);
3150 reg |= rex_r;
3159 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3168 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3174 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3180 offsetof(CPUX86State,fpregs[reg].mmx));
3190 offsetof(CPUX86State,xmm_regs[reg]));
3197 offsetof(CPUX86State,xmm_regs[reg]));
3205 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3211 offsetof(CPUX86State,fpregs[reg].mmx));
3222 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3225 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3233 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3235 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3236 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3237 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3240 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3247 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3249 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3250 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3253 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3261 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3265 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3272 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3275 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3277 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3280 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3281 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3282 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3283 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3288 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3291 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3294 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3295 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3301 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3305 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3312 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3315 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3317 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3320 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3321 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3322 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3323 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3329 offsetof(CPUX86State,fpregs[reg].mmx));
3335 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3343 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3349 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3356 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3359 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3362 reg].XMM_Q(1)));
3367 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3371 offsetof(CPUX86State,fpregs[reg].mmx));
3382 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3386 offsetof(CPUX86State,xmm_regs[reg]));
3392 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3397 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3403 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3407 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3414 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3423 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3468 gen_op_mov_reg_T0(OT_LONG, reg);
3476 gen_op_mov_reg_T0(OT_LONG, reg);
3489 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3506 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3529 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3574 gen_op_mov_reg_T0(ot, reg);
3584 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3588 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3608 reg = ((modrm >> 3) & 7) | rex_r;
3609 gen_op_mov_reg_T0(ot, reg);
3614 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3618 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3625 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3627 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3632 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3649 reg = ((modrm >> 3) & 7) | rex_r;
3650 gen_op_mov_reg_T0(OT_LONG, reg);
3659 reg = ((modrm >> 3) & 7) | rex_r;
3669 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3704 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3727 reg = ((modrm >> 3) & 7) | rex_r;
3744 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3751 gen_op_mov_reg_T0(ot, reg);
3758 reg = ((modrm >> 3) & 7) | rex_r;
3772 reg = ((modrm >> 3) & 7) | rex_r;
3777 xmm_regs[reg].XMM_B(val & 15)));
3786 xmm_regs[reg].XMM_W(val & 7)));
3797 xmm_regs[reg].XMM_L(val & 3)));
3808 xmm_regs[reg].XMM_Q(val & 1)));
3821 xmm_regs[reg].XMM_L(val & 3)));
3835 xmm_regs[reg].XMM_B(val & 15)));
3848 offsetof(CPUX86State,xmm_regs[reg]
3853 xmm_regs[reg].XMM_L(0)));
3857 xmm_regs[reg].XMM_L(1)));
3861 xmm_regs[reg].XMM_L(2)));
3865 xmm_regs[reg].XMM_L(3)));
3877 xmm_regs[reg].XMM_L(val & 3)));
3887 xmm_regs[reg].XMM_Q(val & 1)));
3898 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3907 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3945 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3968 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4045 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4206 reg = ((modrm >> 3) & 7) | rex_r;
4212 } else if (op == OP_XORL && rm == reg) {
4214 /* xor reg, reg optimisation */
4217 gen_op_mov_reg_T0(ot, reg);
4223 gen_op_mov_TN_reg(ot, 1, reg);
4229 reg = ((modrm >> 3) & 7) | rex_r;
4234 } else if (op == OP_XORL && rm == reg) {
4239 gen_op(s, op, ot, reg);
4662 reg = ((modrm >> 3) & 7) | rex_r;
4665 gen_op_mov_TN_reg(ot, 1, reg);
4727 reg = ((modrm >> 3) & 7) | rex_r;
4740 gen_op_mov_TN_reg(ot, 1, reg);
4781 gen_op_mov_reg_T0(ot, reg);
4791 reg = ((modrm >> 3) & 7) | rex_r;
4795 gen_op_mov_TN_reg(ot, 0, reg);
4798 gen_op_mov_reg_T1(ot, reg);
4802 gen_op_mov_TN_reg(ot, 0, reg);
4806 gen_op_mov_reg_T1(ot, reg);
4822 reg = ((modrm >> 3) & 7) | rex_r;
4828 gen_op_mov_v_reg(ot, t1, reg);
5006 reg = b >> 3;
5008 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5010 if (reg == R_SS) {
5011 /* if reg == SS, inhibit interrupts/trace. */
5043 reg = ((modrm >> 3) & 7) | rex_r;
5046 gen_ldst_modrm(s, modrm, ot, reg, 1);
5074 reg = ((modrm >> 3) & 7) | rex_r;
5077 gen_op_mov_reg_T0(ot, reg);
5081 reg = (modrm >> 3) & 7;
5082 if (reg >= 6 || reg == R_CS)
5085 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5086 if (reg == R_SS) {
5087 /* if reg == SS, inhibit interrupts/trace */
5101 reg = (modrm >> 3) & 7;
5103 if (reg >= 6)
5105 gen_op_movl_T0_seg(reg);
5124 reg = ((modrm >> 3) & 7) | rex_r;
5145 gen_op_mov_reg_T0(d_ot, reg);
5153 gen_op_mov_reg_T0(d_ot, reg);
5164 reg = ((modrm >> 3) & 7) | rex_r;
5171 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5245 reg = (b & 7) | REX_B(s);
5247 gen_op_mov_reg_T0(OT_QUAD, reg);
5253 reg = (b & 7) | REX_B(s);
5255 gen_op_mov_reg_T0(ot, reg);
5261 reg = (b & 7) | REX_B(s);
5271 reg = ((modrm >> 3) & 7) | rex_r;
5276 gen_op_mov_TN_reg(ot, 0, reg);
5279 gen_op_mov_reg_T1(ot, reg);
5282 gen_op_mov_TN_reg(ot, 0, reg);
5290 gen_op_mov_reg_T1(ot, reg);
5314 reg = ((modrm >> 3) & 7) | rex_r;
5325 gen_op_mov_reg_T1(ot, reg);
5401 reg = ((modrm >> 3) & 7) | rex_r;
5408 gen_op_mov_TN_reg(ot, 1, reg);
6307 reg = ((modrm >> 3) & 7) | rex_r;
6322 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
6325 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
6331 gen_op_mov_reg_v(ot, reg, t0);
6479 reg = ((modrm >> 3) & 7) | rex_r;
6482 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6540 reg = ((modrm >> 3) & 7) | rex_r;
6553 gen_op_mov_reg_T0(ot, reg);
6710 reg = (modrm >> 3) & 7;
6714 gen_op_mov_TN_reg(ot, 0, reg);
6723 case 0x1c8 ... 0x1cf: /* bswap reg */
6724 reg = (b & 7) | REX_B(s);
6727 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6729 gen_op_mov_reg_T0(OT_QUAD, reg);
6733 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6736 gen_op_mov_reg_T0(OT_LONG, reg);
7223 reg = ((modrm >> 3) & 7) | rex_r;
7232 gen_op_mov_reg_T0(d_ot, reg);
7240 gen_op_mov_reg_T0(d_ot, reg);
7255 reg = (modrm >> 3) & 7;
7264 gen_op_mov_v_reg(ot, t1, reg);
7299 reg = ((modrm >> 3) & 7) | rex_r;
7311 gen_op_mov_reg_v(ot, reg, t0);
7340 case 0x120: /* mov reg, crN */
7341 case 0x122: /* mov crN, reg */
7349 reg = ((modrm >> 3) & 7) | rex_r;
7354 switch(reg) {
7365 gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
7369 gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
7378 case 0x121: /* mov reg, drN */
7379 case 0x123: /* mov drN, reg */
7387 reg = ((modrm >> 3) & 7) | rex_r;
7393 if (reg == 4 || reg == 5 || reg >= 8)
7396 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7398 gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
7402 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7403 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7420 case 0x1c3: /* MOVNTI reg, mem */
7428 reg = ((modrm >> 3) & 7) | rex_r;
7430 gen_ldst_modrm(s, modrm, ot, reg, 1);
7533 reg = ((modrm >> 3) & 7);
7544 gen_op_mov_reg_T0(ot, reg);
