Lines Matching refs:arg
438 #define gen_helper_0i(name, arg) do { \
439 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
2868 static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
2873 tcg_gen_ext_i32_tl(arg, t0);
2877 static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
2879 tcg_gen_ld_tl(arg, cpu_env, off);
2880 tcg_gen_ext32s_tl(arg, arg);
2883 static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
2887 tcg_gen_trunc_tl_i32(t0, arg);
2892 static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
2894 tcg_gen_ext32s_tl(arg, arg);
2895 tcg_gen_st_tl(arg, cpu_env, off);
2898 static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
2909 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
2914 gen_helper_mfc0_mvpcontrol(arg);
2919 gen_helper_mfc0_mvpconf0(arg);
2924 gen_helper_mfc0_mvpconf1(arg);
2934 gen_helper_mfc0_random(arg);
2939 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
2944 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
2949 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
2954 gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
2959 gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
2964 gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
2969 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
2979 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
2980 tcg_gen_ext32s_tl(arg, arg);
2985 gen_helper_mfc0_tcstatus(arg);
2990 gen_helper_mfc0_tcbind(arg);
2995 gen_helper_mfc0_tcrestart(arg);
3000 gen_helper_mfc0_tchalt(arg);
3005 gen_helper_mfc0_tccontext(arg);
3010 gen_helper_mfc0_tcschedule(arg);
3015 gen_helper_mfc0_tcschefback(arg);
3025 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
3026 tcg_gen_ext32s_tl(arg, arg);
3036 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
3037 tcg_gen_ext32s_tl(arg, arg);
3041 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
3051 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
3056 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
3066 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
3071 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
3076 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
3081 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
3086 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
3091 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
3102 gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
3112 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
3113 tcg_gen_ext32s_tl(arg, arg);
3126 gen_helper_mfc0_count(arg);
3141 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
3142 tcg_gen_ext32s_tl(arg, arg);
3152 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
3163 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
3168 gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
3173 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
3178 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
3188 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
3198 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
3199 tcg_gen_ext32s_tl(arg, arg);
3209 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
3214 gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
3224 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
3228 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
3232 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
3236 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
3242 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
3246 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
3256 gen_helper_mfc0_lladdr(arg);
3266 gen_helper_1i(mfc0_watchlo, arg, sel);
3276 gen_helper_1i(mfc0_watchhi, arg, sel);
3288 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
3289 tcg_gen_ext32s_tl(arg, arg);
3301 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
3309 tcg_gen_movi_tl(arg, 0); /* unimplemented */
3315 gen_helper_mfc0_debug(arg); /* EJTAG support */
3319 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
3323 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
3327 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
3331 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
3342 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
3343 tcg_gen_ext32s_tl(arg, arg);
3353 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
3357 // gen_helper_mfc0_performance1(arg);
3361 // gen_helper_mfc0_performance2(arg);
3365 // gen_helper_mfc0_performance3(arg);
3369 // gen_helper_mfc0_performance4(arg);
3373 // gen_helper_mfc0_performance5(arg);
3377 // gen_helper_mfc0_performance6(arg);
3381 // gen_helper_mfc0_performance7(arg);
3389 tcg_gen_movi_tl(arg, 0); /* unimplemented */
3395 tcg_gen_movi_tl(arg, 0); /* unimplemented */
3408 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
3415 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
3428 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
3435 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
3445 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
3446 tcg_gen_ext32s_tl(arg, arg);
3457 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
3475 static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
3489 gen_helper_mtc0_index(arg);
3494 gen_helper_mtc0_mvpcontrol(arg);
3519 gen_helper_mtc0_vpecontrol(arg);
3524 gen_helper_mtc0_vpeconf0(arg);
3529 gen_helper_mtc0_vpeconf1(arg);
3534 gen_helper_mtc0_yqmask(arg);
3539 gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
3544 gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
3549 gen_helper_mtc0_vpeopt(arg);
3559 gen_helper_mtc0_entrylo0(arg);
3564 gen_helper_mtc0_tcstatus(arg);
3569 gen_helper_mtc0_tcbind(arg);
3574 gen_helper_mtc0_tcrestart(arg);
3579 gen_helper_mtc0_tchalt(arg);
3584 gen_helper_mtc0_tccontext(arg);
3589 gen_helper_mtc0_tcschedule(arg);
3594 gen_helper_mtc0_tcschefback(arg);
3604 gen_helper_mtc0_entrylo1(arg);
3614 gen_helper_mtc0_context(arg);
3618 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
3628 gen_helper_mtc0_pagemask(arg);
3633 gen_helper_mtc0_pagegrain(arg);
3643 gen_helper_mtc0_wired(arg);
3648 gen_helper_mtc0_srsconf0(arg);
3653 gen_helper_mtc0_srsconf1(arg);
3658 gen_helper_mtc0_srsconf2(arg);
3663 gen_helper_mtc0_srsconf3(arg);
3668 gen_helper_mtc0_srsconf4(arg);
3679 gen_helper_mtc0_hwrena(arg);
3693 gen_helper_mtc0_count(arg);
3704 gen_helper_mtc0_entryhi(arg);
3714 gen_helper_mtc0_compare(arg);
3726 gen_helper_mtc0_status(arg);
3734 gen_helper_mtc0_intctl(arg);
3741 gen_helper_mtc0_srsctl(arg);
3748 gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
3761 gen_helper_mtc0_cause(arg);
3771 gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
3786 gen_helper_mtc0_ebase(arg);
3796 gen_helper_mtc0_config0(arg);
3806 gen_helper_mtc0_config2(arg);
3833 gen_helper_mtc0_lladdr(arg);
3843 gen_helper_1i(mtc0_watchlo, arg, sel);
3853 gen_helper_1i(mtc0_watchhi, arg, sel);
3865 gen_helper_mtc0_xcontext(arg);
3877 gen_helper_mtc0_framemask(arg);
3891 gen_helper_mtc0_debug(arg); /* EJTAG support */
3898 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
3904 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
3912 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
3918 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
3931 gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
3941 gen_helper_mtc0_performance0(arg);
3945 // gen_helper_mtc0_performance1(arg);
3949 // gen_helper_mtc0_performance2(arg);
3953 // gen_helper_mtc0_performance3(arg);
3957 // gen_helper_mtc0_performance4(arg);
3961 // gen_helper_mtc0_performance5(arg);
3965 // gen_helper_mtc0_performance6(arg);
3969 // gen_helper_mtc0_performance7(arg);
3996 gen_helper_mtc0_taglo(arg);
4003 gen_helper_mtc0_datalo(arg);
4016 gen_helper_mtc0_taghi(arg);
4023 gen_helper_mtc0_datahi(arg);
4034 gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
4045 gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
4071 static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
4082 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
4087 gen_helper_mfc0_mvpcontrol(arg);
4092 gen_helper_mfc0_mvpconf0(arg);
4097 gen_helper_mfc0_mvpconf1(arg);
4107 gen_helper_mfc0_random(arg);
4112 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
4117 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
4122 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
4127 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
4132 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4137 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4142 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
4152 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
4157 gen_helper_mfc0_tcstatus(arg);
4162 gen_helper_mfc0_tcbind(arg);
4167 gen_helper_dmfc0_tcrestart(arg);
4172 gen_helper_dmfc0_tchalt(arg);
4177 gen_helper_dmfc0_tccontext(arg);
4182 gen_helper_dmfc0_tcschedule(arg);
4187 gen_helper_dmfc0_tcschefback(arg);
4197 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
4207 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
4211 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
4221 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
4226 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
4236 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
4241 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
4246 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
4251 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
4256 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
4261 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
4272 gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
4282 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
4295 gen_helper_mfc0_count(arg);
4310 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
4320 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
4331 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
4336 gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
4341 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
4346 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
4356 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
4366 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
4376 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
4381 gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
4391 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
4395 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
4399 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
4403 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
4408 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
4412 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
4422 gen_helper_dmfc0_lladdr(arg);
4432 gen_helper_1i(dmfc0_watchlo, arg, sel);
4442 gen_helper_1i(mfc0_watchhi, arg, sel);
4453 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
4464 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
4472 tcg_gen_movi_tl(arg, 0); /* unimplemented */
4478 gen_helper_mfc0_debug(arg); /* EJTAG support */
4482 // gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
4486 // gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
4490 // gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
4494 // gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
4505 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
4515 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
4519 // gen_helper_dmfc0_performance1(arg);
4523 // gen_helper_dmfc0_performance2(arg);
4527 // gen_helper_dmfc0_performance3(arg);
4531 // gen_helper_dmfc0_performance4(arg);
4535 // gen_helper_dmfc0_performance5(arg);
4539 // gen_helper_dmfc0_performance6(arg);
4543 // gen_helper_dmfc0_performance7(arg);
4551 tcg_gen_movi_tl(arg, 0); /* unimplemented */
4558 tcg_gen_movi_tl(arg, 0); /* unimplemented */
4571 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
4578 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
4591 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
4598 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
4608 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4619 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
4637 static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
4651 gen_helper_mtc0_index(arg);
4656 gen_helper_mtc0_mvpcontrol(arg);
4681 gen_helper_mtc0_vpecontrol(arg);
4686 gen_helper_mtc0_vpeconf0(arg);
4691 gen_helper_mtc0_vpeconf1(arg);
4696 gen_helper_mtc0_yqmask(arg);
4701 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4706 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4711 gen_helper_mtc0_vpeopt(arg);
4721 gen_helper_mtc0_entrylo0(arg);
4726 gen_helper_mtc0_tcstatus(arg);
4731 gen_helper_mtc0_tcbind(arg);
4736 gen_helper_mtc0_tcrestart(arg);
4741 gen_helper_mtc0_tchalt(arg);
4746 gen_helper_mtc0_tccontext(arg);
4751 gen_helper_mtc0_tcschedule(arg);
4756 gen_helper_mtc0_tcschefback(arg);
4766 gen_helper_mtc0_entrylo1(arg);
4776 gen_helper_mtc0_context(arg);
4780 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
4790 gen_helper_mtc0_pagemask(arg);
4795 gen_helper_mtc0_pagegrain(arg);
4805 gen_helper_mtc0_wired(arg);
4810 gen_helper_mtc0_srsconf0(arg);
4815 gen_helper_mtc0_srsconf1(arg);
4820 gen_helper_mtc0_srsconf2(arg);
4825 gen_helper_mtc0_srsconf3(arg);
4830 gen_helper_mtc0_srsconf4(arg);
4841 gen_helper_mtc0_hwrena(arg);
4855 gen_helper_mtc0_count(arg);
4868 gen_helper_mtc0_entryhi(arg);
4878 gen_helper_mtc0_compare(arg);
4892 gen_helper_mtc0_status(arg);
4900 gen_helper_mtc0_intctl(arg);
4907 gen_helper_mtc0_srsctl(arg);
4914 gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
4927 gen_helper_mtc0_cause(arg);
4937 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
4952 gen_helper_mtc0_ebase(arg);
4962 gen_helper_mtc0_config0(arg);
4972 gen_helper_mtc0_config2(arg);
4990 gen_helper_mtc0_lladdr(arg);
5000 gen_helper_1i(mtc0_watchlo, arg, sel);
5010 gen_helper_1i(mtc0_watchhi, arg, sel);
5021 gen_helper_mtc0_xcontext(arg);
5032 gen_helper_mtc0_framemask(arg);
5046 gen_helper_mtc0_debug(arg); /* EJTAG support */
5053 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
5059 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
5065 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
5071 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
5084 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
5094 gen_helper_mtc0_performance0(arg);
5098 // gen_helper_mtc0_performance1(arg);
5102 // gen_helper_mtc0_performance2(arg);
5106 // gen_helper_mtc0_performance3(arg);
5110 // gen_helper_mtc0_performance4(arg);
5114 // gen_helper_mtc0_performance5(arg);
5118 // gen_helper_mtc0_performance6(arg);
5122 // gen_helper_mtc0_performance7(arg);
5149 gen_helper_mtc0_taglo(arg);
5156 gen_helper_mtc0_datalo(arg);
5169 gen_helper_mtc0_taghi(arg);
5176 gen_helper_mtc0_datahi(arg);
5187 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
5198 gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
