Lines Matching defs:rm
1715 UInt rM /* only for debug printing */
1723 DIS(buf, "r%u", rM);
1735 DIS(buf, "r%u, LSL #%u", rM, shift_amt);
1745 UInt rM, UInt rS /* only for debug printing */
1750 // res = amt < 32 ? Rm << amt : 0
1752 // amt in 1..32 ? Rm[32-amt] : 0
1759 Rm[(32-amt) & 31]),
1794 // (Rm << (Rs & 31)) & (((Rs & 255) - 32) >>s 31)
1811 DIS(buf, "r%u, LSL r%u", rM, rS);
1820 UInt rM /* only for debug printing */
1826 // newC = Rm[31]
1834 DIS(buf, "r%u, LSR #0(a.k.a. 32)", rM);
1837 // res = Rm >>u shift_amt
1838 // newC = Rm[shift_amt - 1]
1849 DIS(buf, "r%u, LSR #%u", rM, shift_amt);
1859 UInt rM, UInt rS /* only for debug printing */
1864 // res = amt < 32 ? Rm >>u amt : 0
1866 // amt in 1..32 ? Rm[amt-1] : 0
1873 Rm[(amt-1) & 31]),
1906 // (Rm >>u (Rs & 31)) & (((Rs & 255) - 32) >>s 31)
1923 DIS(buf, "r%u, LSR r%u", rM, rS);
1932 UInt rM /* only for debug printing */
1937 // res = Rm >>s 31
1938 // newC = Rm[31]
1946 DIS(buf, "r%u, ASR #0(a.k.a. 32)", rM);
1949 // res = Rm >>s shift_amt
1950 // newC = Rm[shift_amt - 1]
1961 DIS(buf, "r%u, ASR #%u", rM, shift_amt);
1971 UInt rM, UInt rS /* only for debug printing */
1976 // res = amt < 32 ? Rm >>s amt : Rm >>s 31
1978 // amt in 1..32 ? Rm[amt-1] : Rm[31]
1984 Rm[31],
1985 Rm[(amt-1) & 31])
2024 // (Rm >>s (amt <u 32 ? amt : 31))
2038 DIS(buf, "r%u, ASR r%u", rM, rS);
2047 UInt rM, UInt rS /* only for debug printing */
2052 // shop = Rm `ror` (amt & 31)
2053 // shco = amt == 0 ? oldC : Rm[(amt-1) & 31]
2102 DIS(buf, "r%u, ROR r#%u", rM, rS);
2128 UInt rM /* only for debug printing */
2138 buf, res, newC, rMt, shift_amt, rM
2144 buf, res, newC, rMt, shift_amt, rM
2150 buf, res, newC, rMt, shift_amt, rM
2159 // res = (oldC << 31) | (Rm >>u 1)
2160 // newC = Rm[0]
2170 DIS(buf, "r%u, RRX", rM);
2173 // res = Rm `ror` shift_amt
2174 // newC = Rm[shift_amt - 1]
2188 DIS(buf, "r%u, ROR #%u", rM, shift_amt);
2221 UInt rM, /* only for debug printing */
2229 buf, res, newC, rMt, rSt, rM, rS
2235 buf, res, newC, rMt, rSt, rM, rS
2241 buf, res, newC, rMt, rSt, rM, rS
2247 buf, res, newC, rMt, rSt, rM, rS
2312 /* Rm (3:0) shifted (6:5) by immediate (11:7) */
2314 UInt rM = (insn_11_0 >> 0) & 0xF;
2318 assign(rMt, getIRegA(rM));
2323 buf, shop, shco, rMt, how, shift_amt, rM
2330 /* Rm (3:0) shifted (6:5) by Rs (11:8) */
2331 UInt rM = (insn_11_0 >> 0) & 0xF;
2341 assign(rMt, getIRegA(rM));
2345 buf, shop, shco, rMt, how, rSt, rM, rS
2376 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
2382 vassert(rM < 16);
2390 index = binop(Iop_Shl32, getIRegA(rM), mkU8(imm5));
2391 DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5);
2398 index = binop(Iop_Shr32, getIRegA(rM), mkU8(imm5));
2401 rN, opChar, rM, imm5 == 0 ? 32 : imm5);
2407 index = binop(Iop_Sar32, getIRegA(rM), mkU8(31));
2410 index = binop(Iop_Sar32, getIRegA(rM), mkU8(imm5));
2413 rN, opChar, rM, imm5 == 0 ? 32 : imm5);
2419 assign(rmT, getIRegA(rM));
2424 DIS(buf, "[r%u, %cr%u, RRX]", rN, opChar, rM);
2427 assign(rmT, getIRegA(rM));
2432 DIS(buf, "[r%u, %cr%u, ROR #%u]", rN, opChar, rM, imm5);
2463 IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM,
2468 vassert(rM < 16);
2470 IRExpr* index = getIRegA(rM);
2471 DIS(buf, "[r%u, %c r%u]", rN, opChar, rM);
7938 UInt rM = INSN(3,0);
7958 assign(initialRm, isT ? getIRegT(rM) : getIRegA(rM));
8000 if (rM != 13 && rM != 15) {
8001 DIP(", r%u\n", rM);
8003 DIP("%s\n", (rM != 15) ? "!" : "");
8097 if (rM != 13 && rM != 15) {
8098 DIP(", r%u\n", rM);
8100 DIP("%s\n", (rM != 15) ? "!" : "");
8104 if (rM != 15) {
8105 if (rM == 13) {
8184 if (rM != 15) {
8185 if (rM == 13) {
8217 if (rM != 13 && rM != 15) {
8218 DIP(", r%u\n", rM);
8220 DIP("%s\n", (rM != 15) ? "!" : "");
8418 /* ------------ smulwb<y><c> <Rd>,<Rn>,<Rm> ------------- */
8419 /* ------------ smulwt<y><c> <Rd>,<Rn>,<Rm> ------------- */
8479 /* ------------ pkhbt<c> Rd, Rn, Rm {,LSL #imm} ------------- */
8480 /* ------------ pkhtb<c> Rd, Rn, Rm {,ASR #imm} ------------- */
8717 /* -------------- uadd16<c> <Rd>,<Rn>,<Rm> -------------- */
8766 /* -------------- sadd16<c> <Rd>,<Rn>,<Rm> -------------- */
8816 /* ---------------- usub16<c> <Rd>,<Rn>,<Rm> ---------------- */
8866 /* -------------- ssub16<c> <Rd>,<Rn>,<Rm> -------------- */
8916 /* ----------------- uadd8<c> <Rd>,<Rn>,<Rm> ---------------- */
8965 /* ------------------- sadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9015 /* ------------------- usub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9065 /* ------------------- ssub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9115 /* ------------------ qadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9160 /* ------------------ qsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
9205 /* ------------------ uqadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9250 /* ------------------ uqsub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9295 /* ----------------- uhadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9340 /* ----------------- shadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9385 /* ------------------ qadd16<c> <Rd>,<Rn>,<Rm> ------------------ */
9430 /* ------------------ qsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
9481 /* ------------------- qsax<c> <Rd>,<Rn>,<Rm> ------------------- */
9552 /* ------------------- qasx<c> <Rd>,<Rn>,<Rm> ------------------- */
9620 /* ------------------- sasx<c> <Rd>,<Rn>,<Rm> ------------------- */
9694 /* --------------- smuad, smuadx<c><Rd>,<Rn>,<Rm> --------------- */
9695 /* --------------- smsad, smsadx<c><Rd>,<Rn>,<Rm> --------------- */
9773 /* --------------- smlad{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
9774 /* --------------- smlsd{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
9864 /* ----- smlabb, smlabt, smlatb, smlatt <Rd>,<Rn>,<Rm>,<Ra> ----- */
9934 /* ----- smlawb, smlawt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10005 /* ------------------- sel<c> <Rd>,<Rn>,<Rm> -------------------- */
10093 /* ----------------- uxtab16<c> Rd,Rn,Rm{,rot} ------------------ */
10156 /* --------------- usad8 Rd,Rn,Rm ---------------- */
10157 /* --------------- usada8 Rd,Rn,Rm,Ra ---------------- */
10159 UInt rD = 99, rN = 99, rM = 99, rA = 99;
10167 rM = INSNT1(3,0);
10168 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && rA != 13)
10176 rM = INSNA(11,8);
10178 if (rD != 15 && rN != 15 && rM != 15 /* but rA can be 15 */)
10186 IRExpr* rMe = isT ? getIRegT(rM) : getIRegA(rM);
10199 nCC(conq), rD, rN, rM );
10202 nCC(conq), rD, rN, rM, rA );
10835 // VMOV sD, sD+1, rN, rM
10839 UInt rM = INSN(19,16);
10840 if (rM == 15 || rN == 15 || (isT && (rM == 13 || rN == 13))
10848 unop(Iop_ReinterpI32asF32, isT ? getIRegT(rM) : getIRegA(rM)),
10851 nCC(conq), sD, sD + 1, rN, rM);
10856 // VMOV rN, rM, sD, sD+1
10860 UInt rM = INSN(19,16);
10861 if (rM == 15 || rN == 15 || (isT && (rM == 13 || rN == 13))
10862 || sD == 31 || rN == rM) {
10869 putIRegT(rM, res1, condT);
10872 putIRegA(rM, res1, condT, Ijk_Boring);
10875 nCC(conq), rN, rM, sD, sD + 1);
11110 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
11113 putDReg(dD, triop(Iop_AddF64, rm,
11115 triop(Iop_MulF64, rm
11121 putDReg(dD, triop(Iop_AddF64, rm,
11124 triop(Iop_MulF64, rm, getDReg(dN),
11130 putDReg(dD, triop(Iop_AddF64, rm,
11132 triop(Iop_MulF64, rm, getDReg(dN),
11138 putDReg(dD, triop(Iop_AddF64, rm,
11141 triop(Iop_MulF64, rm, getDReg(dN),
11147 putDReg(dD, triop(Iop_MulF64, rm, getDReg(dN), getDReg(dM)),
11153 triop(Iop_MulF64, rm, getDReg(dN),
11159 putDReg(dD, triop(Iop_AddF64, rm, getDReg(dN), getDReg(dM)),
11164 putDReg(dD, triop(Iop_SubF64, rm, getDReg(dN), getDReg(dM)),
11169 putDReg(dD, triop(Iop_DivF64, rm, getDReg(dN), getDReg(dM)),
11279 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
11280 putDReg(dD, binop(Iop_SqrtF64, rm, getDReg(dM)), condT);
11575 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
11578 putFReg(fD, triop(Iop_AddF32, rm,
11580 triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
11585 putFReg(fD, triop(Iop_AddF32, rm,
11588 triop(Iop_MulF32, rm, getFReg(fN),
11594 putFReg(fD, triop(Iop_AddF32, rm,
11596 triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
11601 putFReg(fD, triop(Iop_AddF32, rm,
11604 triop(Iop_MulF32, rm,
11611 putFReg(fD, triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM)),
11617 triop(Iop_MulF32, rm, getFReg(fN),
11623 putFReg(fD, triop(Iop_AddF32, rm, getFReg(fN), getFReg(fM)),
11628 putFReg(fD, triop(Iop_SubF32, rm, getFReg(fN), getFReg(fM)),
11633 putFReg(fD, triop(Iop_DivF32, rm, getFReg(fN), getFReg(fM)),
11750 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
11751 putFReg(fD, binop(Iop_SqrtF32, rm, getFReg(fM)), condT);
11918 UInt rM = INSN(3,0);
11922 if (rM != 15) {
11923 IRExpr* eaE = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM,
12486 A5-22 1 | 32 cond 0111 UBOL Rn Rd imm5 sh2 0 Rm
12488 A5-26 2 | 32 cond 0111 UB1L Rn Rd imm5 sh2 0 Rm
12490 A5-32 3 | 32 cond 0110 UB0L Rn Rd imm5 sh2 0 Rm
12498 32 Rn +/- Rm sh2 imm5
12531 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
12546 if (rM == 15) goto after_load_store_ubyte_or_word;
12553 if (rM == 15) goto after_load_store_ubyte_or_word;
12555 if (rN == rM) goto after_load_store_ubyte_or_word;
12579 eaE = mk_EA_reg_plusminus_shifted_reg( rN, bU, rM, sh2, imm5,
12707 A5-38 1 | 32 cond 0001 U00L Rn Rd 0000 1SH1 Rm
12709 A5-42 2 | 32 cond 0001 U01L Rn Rd 0000 1SH1 Rm
12711 A5-46 3 | 32 cond 0000 U00L Rn Rd 0000 1SH1 Rm
12719 32 Rn +/- Rm
12753 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
12768 /* Require 11:8 == 0 for Rn +/- Rm cases */
12779 if (rM == 15) goto after_load_store_sbyte_or_hword;
12786 if (rM == 15) goto after_load_store_sbyte_or_hword;
12788 if (rN == rM) goto after_load_store_sbyte_or_hword;
12812 eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
13053 UInt rM = INSN(3,0);
13054 // we don't decode the case (link && rM == 15), as that's
13056 if (!(link && rM == 15)) {
13060 // rM contains an interworking address exactly as we require
13063 assign( dst, getIRegA(rM) );
13070 : (rM == 14 ? Ijk_Ret : Ijk_Boring);
13073 DIP("b%sx r%u\n", link ? "l" : "", rM);
13075 DIP("b%sx%s r%u\n", link ? "l" : "", nCC(INSN_COND), rM);
13079 /* else: (link && rM == 15): just fall through */
13093 UInt rM = INSN(3,0);
13096 assign(arg, getIRegA(rM));
13104 DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
13116 UInt rM = INSN(3,0);
13117 if (rD == 15 || rM == 15 || rS == 15) {
13125 assign( argL, getIRegA(rM));
13144 bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS);
13158 UInt rM = INSN(3,0);
13164 if (rD == 15 || rM == 15 || rS == 15 || rN == 15) {
13173 assign( argL, getIRegA(rM));
13197 rM, rS, rN);
13210 UInt rM = INSN(3,0);
13212 if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo) {
13223 assign( argL, getIRegA(rM));
13246 nCC(INSN_COND), rDlo, rDhi, rM, rS);
13259 UInt rM = INSN(3,0);
13261 if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo) {
13273 assign( argL, getIRegA(rM));
13299 rDlo, rDhi, rM, rS);
13383 UInt rM = INSN(3,0);
13390 if (rD == 15 || rN == 15 || rM == 15 || rN == rM || rN == rD) {
13400 assign(tNew, getIRegA(rM));
13422 isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
13590 UInt rM = INSN(3,0);
13596 assign(srcT, getIRegA(rM));
13643 DIP("%s%s r%u, r%u, ROR #%u\n", nm, nCC(INSN_COND), rD, rM, rot);
13735 A5-38 1 | 32 cond 0001 U000 Rn Rd 0000 11S1 Rm
13737 A5-42 2 | 32 cond 0001 U010 Rn Rd 0000 11S1 Rm
13739 A5-46 3 | 32 cond 0000 U000 Rn Rd 0000 11S1 Rm
13747 32 Rn +/- Rm
13781 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
13790 /* Require 11:8 == 0 for Rn +/- Rm cases */
13801 if (rM == 15) goto after_load_store_doubleword;
13809 if (rM == 15) goto after_load_store_doubleword;
13811 if (rN == rM) goto after_load_store_doubleword;
13836 eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
13913 UInt rM = INSN(3,0);
13916 if (rN == 15/*it's {S,U}XTB*/ || rD == 15 || rM == 15) {
13922 assign(srcR, getIRegA(rM));
13931 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
13943 UInt rM = INSN(3,0);
13946 if (rN == 15/*it's {S,U}XTH*/ || rD == 15 || rM == 15) {
13952 assign(srcR, getIRegA(rM));
13962 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
13972 UInt rM = INSN(3,0);
13974 if (rM != 15 && rD != 15) {
13976 assign(rMt, getIRegA(rM));
13980 nCC(INSN_COND), rD, rM);
13988 UInt rM = INSN(3,0);
13989 if (rD != 15 && rM != 15) {
13991 assign(arg, getIRegA(rM));
13994 DIP("rbit r%u, r%u\n", rD, rM);
14005 UInt rM = INSN(11,8);
14007 if (rD != 15 && rM != 15 && rN != 15) {
14011 binop(Iop_MullS32, getIRegA(rN), getIRegA(rM)),
14015 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM);
14647 /* ---------------- CMP Rn, Rm ---------------- */
14650 UInt rM = INSN0(5,3);
14654 assign( argR, getIRegT(rM) );
14658 DIP("%s r%u, r%u\n", isCMN ? "cmn" : "cmp", rN, rM);
14663 /* ---------------- TST Rn, Rm ---------------- */
14665 UInt rM = INSN0(5,3);
14671 assign( res, binop(Iop_And32, getIRegT(rN), getIRegT(rM)) );
14674 DIP("tst r%u, r%u\n", rN, rM);
14679 /* ---------------- NEGS Rd, Rm ---------------- */
14680 /* Rd = -Rm */
14681 UInt rM = INSN0(5,3);
14685 assign(arg, getIRegT(rM));
14690 DIP("negs r%u, r%u\n", rD, rM);
14695 /* ---------------- MVNS Rd, Rm ---------------- */
14696 /* Rd = ~Rm */
14697 UInt rM = INSN0(5,3);
14704 assign(res, unop(Iop_Not32, getIRegT(rM)));
14709 DIP("mvns r%u, r%u\n", rD, rM);
14714 /* ---------------- ORRS Rd, Rm ---------------- */
14717 /* ---------------- ANDS Rd, Rm ---------------- */
14720 /* ---------------- EORS Rd, Rm ---------------- */
14723 /* ---------------- MULS Rd, Rm ---------------- */
14726 /* Rd = Rd `op` Rm */
14727 UInt rM = INSN0(5,3);
14734 assign( res, binop(anOp, getIRegT(rD), getIRegT(rM) ));
14740 DIP("%s r%u, r%u\n", anOpNm, rD, rM);
14745 /* ---------------- BICS Rd, Rm ---------------- */
14746 /* Rd = Rd & ~Rm */
14747 UInt rM = INSN0(5,3);
14755 unop(Iop_Not32, getIRegT(rM) )));
14761 DIP("bics r%u, r%u\n", rD, rM);
14766 /* ---------------- ADCS Rd, Rm ---------------- */
14767 /* Rd = Rd + Rm + oldC */
14768 UInt rM = INSN0(5,3);
14775 assign(argR, getIRegT(rM));
14784 DIP("adcs r%u, r%u\n", rD, rM);
14789 /* ---------------- SBCS Rd, Rm ---------------- */
14790 /* Rd = Rd - Rm - (oldC ^ 1) */
14791 UInt rM = INSN0(5,3);
14798 assign(argR, getIRegT(rM));
14807 DIP("sbcs r%u, r%u\n", rD, rM);
14812 /* ---------------- UXTB Rd, Rm ---------------- */
14813 /* Rd = 8Uto32(Rm) */
14814 UInt rM = INSN0(5,3);
14816 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFF)),
14818 DIP("uxtb r%u, r%u\n", rD, rM);
14823 /* ---------------- SXTB Rd, Rm ---------------- */
14824 /* Rd = 8Sto32(Rm) */
14825 UInt rM = INSN0(5,3);
14828 binop(Iop_Shl32, getIRegT(rM), mkU8(24)),
14831 DIP("sxtb r%u, r%u\n", rD, rM);
14836 /* ---------------- UXTH Rd, Rm ---------------- */
14837 /* Rd = 16Uto32(Rm) */
14838 UInt rM = INSN0(5,3);
14840 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFFFF)),
14842 DIP("uxth r%u, r%u\n", rD, rM);
14847 /* ---------------- SXTH Rd, Rm ---------------- */
14848 /* Rd = 16Sto32(Rm) */
14849 UInt rM = INSN0(5,3);
14852 binop(Iop_Shl32, getIRegT(rM), mkU8(16)),
14855 DIP("sxth r%u, r%u\n", rD, rM);
14918 /* ---------------- REV Rd, Rm ---------------- */
14919 /* ---------------- REV16 Rd, Rm ---------------- */
14920 UInt rM = INSN0(5,3);
14924 assign(arg, getIRegT(rM));
14927 DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM);
14960 /* ---------------- BX rM ---------------- */
14964 UInt rM = (INSN0(6,6) << 3) | INSN0(5,3);
14971 if (rM <= 14) {
14972 assign( dst, getIRegT(rM) );
14974 vassert(rM == 15);
14978 irsb->jumpkind = rM == 14 ? Ijk_Ret : Ijk_Boring;
14980 DIP("bx r%u (possibly switch to ARM mode)\n", rM);
14986 /* ---------------- BLX rM ---------------- */
14987 /* Branch and link to interworking address in rM. */
14990 UInt rM = (INSN0(6,6) << 3) | INSN0(5,3);
14992 if (rM <= 14) {
14998 assign( dst, getIRegT(rM) );
15004 DIP("blx r%u (possibly switch to ARM mode)\n", rM);
15045 /* ---------------- ADD(HI) Rd, Rm ---------------- */
15048 UInt rM = (h2 << 3) | INSN0(5,3);
15051 if (rD == 15 && rM == 15) {
15055 assign( res, binop(Iop_Add32, getIRegT(rD), getIRegT(rM) ));
15070 DIP("add(hi) r%u, r%u\n", rD, rM);
15077 /* ---------------- CMP(HI) Rd, Rm ---------------- */
15080 UInt rM = (h2 << 3) | INSN0(5,3);
15086 assign( argR, getIRegT(rM) );
15089 DIP("cmphi r%u, r%u\n", rN, rM);
15096 /* ---------------- MOV(HI) Rd, Rm ---------------- */
15099 UInt rM = (h2 << 3) | INSN0(5,3);
15102 Rm are "low" registers, but newer versions allow it. */
15105 assign( val, getIRegT(rM) );
15117 irsb->jumpkind = rM == 14 ? Ijk_Ret : Ijk_Boring;
15120 DIP("mov r%u, r%u\n", rD, rM);
15351 /* ---------------- ADDS Rd, Rn, Rm ---------------- */
15352 /* ---------------- SUBS Rd, Rn, Rm ---------------- */
15353 UInt rM = INSN0(8,6);
15360 rM) );
15366 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
15372 /* ------------- LDR Rd, [Rn, Rm] ------------- */
15373 /* ------------- STR Rd, [Rn, Rm] ------------- */
15374 /* LDR/STR Rd, [Rn + Rm] */
15377 UInt rM = INSN0(8,6);
15384 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
15393 DIP("%s r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
15399 /* ------------- LDRH Rd, [Rn, Rm] ------------- */
15400 /* ------------- STRH Rd, [Rn, Rm] ------------- */
15401 /* LDRH/STRH Rd, [Rn + Rm] */
15404 UInt rM = INSN0(8,6);
15411 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
15421 DIP("%sh r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
15426 /* ------------- LDRSH Rd, [Rn, Rm] ------------- */
15427 /* LDRSH Rd, [Rn + Rm] */
15430 UInt rM = INSN0(8,6);
15436 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
15442 DIP("ldrsh r%u, [r%u, r%u]\n", rD, rN, rM);
15447 /* ------------- LDRSB Rd, [Rn, Rm] ------------- */
15448 /* LDRSB Rd, [Rn + Rm] */
15451 UInt rM = INSN0(8,6);
15457 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
15463 DIP("ldrsb r%u, [r%u, r%u]\n", rD, rN, rM);
15469 /* ------------- LDRB Rd, [Rn, Rm] ------------- */
15470 /* ------------- STRB Rd, [Rn, Rm] ------------- */
15471 /* LDRB/STRB Rd, [Rn + Rm] */
15474 UInt rM = INSN0(8,6);
15481 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
15491 DIP("%sb r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
15806 /* ---------------- LSLS Rd, Rm, #imm5 ---------------- */
15807 /* ---------------- LSRS Rd, Rm, #imm5 ---------------- */
15808 /* ---------------- ASRS Rd, Rm, #imm5 ---------------- */
15810 UInt rM = INSN0(5,3);
15817 assign(rMt, getIRegT(rM));
15824 dis_buf, &res, &resC, rMt, imm5, rM
15830 dis_buf, &res, &resC, rMt, imm5, rM
15836 dis_buf, &res, &resC, rMt, imm5, rM
15848 DIP("%ss r%u, r%u, #%u\n", wot, rD, rM, imm5);
15946 UInt rM = INSN1(3,0);
15948 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
15952 binop(Iop_MullS32, getIRegT(rN), getIRegT(rM)),
15956 bitR ? "r" : "", rD, rN, rM);
16367 /* ---------- (T3) ADD{S}.W Rd, Rn, Rm, {shift} ---------- */
16368 /* ---------- (T3) SUB{S}.W Rd, Rn, Rm, {shift} ---------- */
16369 /* ---------- (T3) RSB{S}.W Rd, Rn, Rm, {shift} ---------- */
16377 UInt rM = INSN1(3,0);
16382 Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
16411 assign(rMt, getIRegT(rM));
16415 dis_buf, &argR, NULL, rMt, how, imm5, rM
16446 /* ---------- (T3) ADC{S}.W Rd, Rn, Rm, {shift} ---------- */
16447 /* ---------- (T2) SBC{S}.W Rd, Rn, Rm, {shift} ---------- */
16456 UInt rM = INSN1(3,0);
16457 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
16466 assign(rMt, getIRegT(rM));
16473 dis_buf, &argR, NULL, rMt, how, imm5, rM
16511 /* ---------- (T3) AND{S}.W Rd, Rn, Rm, {shift} ---------- */
16512 /* ---------- (T3) ORR{S}.W Rd, Rn, Rm, {shift} ---------- */
16513 /* ---------- (T3) EOR{S}.W Rd, Rn, Rm, {shift} ---------- */
16514 /* ---------- (T3) BIC{S}.W Rd, Rn, Rm, {shift} ---------- */
16515 /* ---------- (T1) ORN{S}.W Rd, Rn, Rm, {shift} ---------- */
16525 UInt rM = INSN1(3,0);
16526 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
16548 assign(rMt, getIRegT(rM));
16554 dis_buf, &argR, bS ? &oldC : NULL, rMt, how, imm5, rM
16580 /* -------------- (T?) LSL{S}.W Rd, Rn, Rm -------------- */
16581 /* -------------- (T?) LSR{S}.W Rd, Rn, Rm -------------- */
16582 /* -------------- (T?) ASR{S}.W Rd, Rn, Rm -------------- */
16583 /* -------------- (T?) ROR{S}.W Rd, Rn, Rm -------------- */
16590 UInt rM = INSN1(3,0);
16592 Bool valid = !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rD);
16602 assign(rMt, getIRegT(rM));
16605 rNt, how, rMt, rN, rM
16615 nm, bS ? "s" : "", rD, rN, rM);
16657 /* -------------- (T?) TST.W Rn, Rm, {shift} -------------- */
16658 /* -------------- (T?) TEQ.W Rn, Rm, {shift} -------------- */
16665 UInt rM = INSN1(3,0);
16666 if (!isBadRegT(rN) && !isBadRegT(rM)) {
16676 assign(rMt, getIRegT(rM));
16681 dis_buf, &argR, &oldC, rMt, how, imm5, rM
16698 /* -------------- (T3) CMP.W Rn, Rm, {shift} -------------- */
16699 /* -------------- (T2) CMN.W Rn, Rm, {shift} -------------- */
16706 UInt rM = INSN1(3,0);
16707 if (!isBadRegT(rN) && !isBadRegT(rM)) {
16716 assign(rMt, getIRegT(rM));
16720 dis_buf, &argR, NULL, rMt, how, imm5, rM
16982 op Rt, [Rn, Rm, LSL #imm8]
17017 UInt rM = INSN1(3,0);
17025 if (rN == 15 || isBadRegT(rT) || isBadRegT(rM))
17029 if (rN == 15 || isBadRegT(rM))
17053 binop(Iop_Shl32, getIRegT(rM), mkU8(imm2)) ));
17112 nm, rT, rN, rM, imm2);
17419 UInt rM = INSN1(3,0);
17421 if (bH/*ATC*/ || (rN != 13 && !isBadRegT(rM))) {
17431 bH ? binop(Iop_Shl32, getIRegT(rM), mkU8(1))
17432 : getIRegT(rM));
17452 bH ? 'h' : 'b', rN, rM, bH ? ", LSL #1" : "");
17512 UInt rM = INSN1(3,0);
17514 if (!isBadRegT(rD) && !isBadRegT(rM)) {
17519 assign(srcT, getIRegT(rM));
17571 DIP("%s r%u, r%u, ror #%u\n", nm, rD, rM, 8 * rot);
17576 /* -------------- MUL.W Rd, Rn, Rm -------------- */
17581 UInt rM = INSN1(3,0);
17582 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
17584 assign(res, binop(Iop_Mul32, getIRegT(rN), getIRegT(rM)));
17586 DIP("mul.w r%u, r%u, r%u\n", rD, rN, rM);
17598 UInt rM = INSN1(3,0);
17600 && !isBadRegT(rN) && !isBadRegT(rM) && rDlo != rDhi) {
17603 getIRegT(rN), getIRegT(rM)));
17607 isU ? 'u' : 's', rDlo, rDhi, rN, rM);
17619 UInt rM = INSN1(3,0);
17621 && !isBadRegT(rM) && !isBadRegT(rA)) {
17627 binop(Iop_Mul32, getIRegT(rN), getIRegT(rM))));
17630 isMLA ? "mla" : "mls", rD, rN, rM, rA);
17660 UInt rM = INSN1(3,0);
17662 && !isBadRegT(rM) && rDhi != rDlo) {
17671 assign( argL, getIRegT(rM));
17682 isS ? 's' : 'u', rDlo, rDhi, rN, rM);
17756 UInt rM = INSN1(3,0);
17758 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
17762 assign(srcR, getIRegT(rM));
17771 isU ? 'u' : 's', rD, rN, rM, rot);
17785 UInt rM = INSN1(3,0);
17787 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
17791 assign(srcR, getIRegT(rM));
17800 isU ? 'u' : 's', rD, rN, rM, rot);
18109 UInt rM = INSN1(3,0);
18112 if (!isBadRegT(rM)) {
18113 DIP("pld%s [r%u, r%u, lsl %d]\n", bW ? "w" : "", rN, rM, imm2);
