Lines Matching defs:shift
1298 Int i, shift[6];
1308 shift[i] = 1 << i;
1324 binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])),
1333 shift[i] = 1 << i;
1348 binop( Iop_Shr64, mkexpr( old ), mkU8( shift[i] ) ),
1377 because otherwise the Shr is a shift by the word size when
2141 /* The shift amount is guaranteed to be in 0 .. 63 inclusive.
2144 /* This term valid for shift amount < 32 only */
2159 /* shift amt > 31 ? */
2170 0. Since the shift amount is known to be in the range
2260 /* The shift amount is guaranteed to be in 0 .. 31 inclusive.
2263 /* This term valid for shift amount < 31 only */
2279 /* shift amt > 31 ? */
2290 Since the shift amount is known to be in the range 0 .. 31
2314 /* The shift amount is guaranteed to be in 0 .. 63 inclusive.
2317 /* This term valid for shift amount < 63 only */
2333 /* shift amt > 63 ? */
2345 Since the shift amount is known to be in the range 0 .. 63
3958 * to determine which bit of rB to use for the perm bit, and then we shift
4217 shift left, PPC32 p501 */
4224 unsigned shift right, PPC32 p501 */
4319 unsigned shift-right by n */
4336 shift-left by n */
4891 Int i, shift = 24;
4908 shift = 24;
4910 /* rD |= (8Uto32(*(EA+i))) << shift */
4911 vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24);
4926 mkU8(toUChar(shift))
4932 shift -= 8;
4942 Int i, shift = 24;
4958 shift = 24;
4960 /* *(EA+i) = 32to8(rS >> shift) */
4961 vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24);
4967 mkU8(toUChar(shift))))
4969 shift -= 8;
5893 Integer Shift Instructions
5923 case 0x018: { // slw (Shift Left Word, PPC32 p505)
5947 case 0x318: { // sraw (Shift Right Alg Word, PPC32 p506)
5978 case 0x338: // srawi (Shift Right Alg Word Immediate, PPC32 p507)
5999 case 0x218: // srw (Shift Right Word, PPC32 p508)
6026 case 0x01B: // sld (Shift Left DWord, PPC64 p568)
6048 case 0x31A: { // srad (Shift Right Alg DWord, PPC64 p570)
6089 case 0x21B: // srd (Shift Right DWord, PPC64 p574)
11025 case 0x8: // xxsldwi (VSX Shift Left Double by Word Immediate)
11149 case 0x006: { // lvsl (Load Vector for Shift Left, AV p123)
11182 case 0x026: { // lvsr (Load Vector for Shift Right, AV p125)
12208 AltiVec Shift/Rotate Instructions
12247 /* Shift Left */
12248 case 0x104: // vslb (Shift Left Integer B, AV p240)
12253 case 0x144: // vslh (Shift Left Integer HW, AV p242)
12258 case 0x184: // vslw (Shift Left Integer W, AV p244)
12263 case 0x1C4: { // vsl (Shift Left, AV p239)
12273 case 0x40C: { // vslo (Shift Left by Octet, AV p243)
12285 /* Shift Right */
12286 case 0x204: // vsrb (Shift Right B, AV p256)
12291 case 0x244: // vsrh (Shift Right HW, AV p257)
12296 case 0x284: // vsrw (Shift Right W, AV p259)
12301 case 0x2C4: { // vsr (Shift Right, AV p251)
12311 case 0x304: // vsrab (Shift Right Alg B, AV p253)
12316 case 0x344: // vsrah (Shift Right Alg HW, AV p254)
12321 case 0x384: // vsraw (Shift Right Alg W, AV p255)
12326 case 0x44C: { // vsro (Shift Right by Octet, AV p258)
12413 case 0x2C: // vsldoi (Shift Left Double by Octet Imm, AV p241)
12969 // finally, just shift gt,lt to correct position
13911 /* Integer Shift Instructions */
13917 /* 64bit Integer Shift Instructions */
14176 /* AV Rotate, Shift */
