Lines Matching defs:shift
646 ... base(%rbp, %tmp, shift) ...
951 /* Perhaps a shift op? */
1002 /* Now consider the shift amount. If it's a literal, we
1268 Int shift = 0;
1271 case Iop_MullS32: shr_op = Ash_SAR; shift = 32; break;
1272 case Iop_MullS16: shr_op = Ash_SAR; shift = 48; break;
1273 case Iop_MullS8: shr_op = Ash_SAR; shift = 56; break;
1274 case Iop_MullU32: shr_op = Ash_SHR; shift = 32; break;
1275 case Iop_MullU16: shr_op = Ash_SHR; shift = 48; break;
1276 case Iop_MullU8: shr_op = Ash_SHR; shift = 56; break;
1282 addInstr(env, AMD64Instr_Sh64(Ash_SHL, shift, a32));
1283 addInstr(env, AMD64Instr_Sh64(Ash_SHL, shift, b32));
1284 addInstr(env, AMD64Instr_Sh64(shr_op, shift, a32));
1285 addInstr(env, AMD64Instr_Sh64(shr_op, shift, b32));
1525 Int shift = 0;
1527 case Iop_16HIto8: shift = 8; break;
1528 case Iop_32HIto16: shift = 16; break;
1529 case Iop_64HIto32: shift = 32; break;
1533 addInstr(env, AMD64Instr_Sh64(Ash_SHR, shift, dst));
1905 UInt shift = imm8->Iex.Const.con->Ico.U8;
1909 vassert(shift == 0 || shift == 1 || shift == 2 || shift == 3);
1910 return AMD64AMode_IRRS(offset, r1, r2, shift);
1921 UInt shift = e->Iex.Binop.arg2->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
1922 if (shift == 1 || shift == 2 || shift == 3) {
1925 return AMD64AMode_IRRS(0, r1, r2, shift);
2567 //.. to be shifted into %hi:%lo, and the shift amount into
2571 //.. -- shift amt %cl % 32
2573 //.. -- shift amt %cl % 32
2575 //.. Now, if (shift amount % 64) is in the range 32 .. 63,
2594 //.. /* Ok. Now shift amt is in %ecx, and value is in tHi/tLo
2610 //.. to be shifted into %hi:%lo, and the shift amount into
2614 //.. -- shift amt %cl % 32
2616 //.. -- shift amt %cl % 32
2618 //.. Now, if (shift amount % 64) is in the range 32 .. 63,
2637 //.. /* Ok. Now shift amt is in %ecx, and value is in tHi/tLo
