Lines Matching defs:rreg
79 HReg rreg;
95 /* Which rreg is this for? */
96 HReg rreg;
106 rreg has the same value as the spill slot for the associated
108 spill store or reload for this rreg. */
130 rreg" is the main beneficiary.
133 associated with any rreg, that entry can be set to INVALID_RREG_NO.
352 HReg rreg, vreg, vregS, vregD;
390 /* The vreg -> rreg map constructed and then applied to each
428 (*ppReg)(rreg_state[z].rreg); \
469 rreg_state[j].rreg = available_real_regs[j];
482 /* --------- Stage 2: compute rreg live ranges. --------- */
506 /* ------ start of SET UP TO COMPUTE RREG LIVE RANGES ------ */
518 each rreg. Sigh. */
528 /* ------ end of SET UP TO COMPUTE RREG LIVE RANGES ------ */
602 /* ------ start of DEAL WITH RREG LIVE RANGES ------ */
612 rreg = reg_usage.hreg[j];
615 if (hregIsVirtual(rreg))
618 /* Furthermore, we're not interested in this rreg unless it's
623 if (available_real_regs[k] == rreg)
640 vex_printf("\nOFFENDING RREG = ");
647 "first event for rreg is Read");
653 vex_printf("\nOFFENDING RREG = ");
660 "first event for rreg is Modify");
674 rreg_lrs_la[rreg_lrs_used].rreg = rreg;
682 /* ------ end of DEAL WITH RREG LIVE RANGES ------ */
688 /* ------ start of FINALISE RREG LIVE RANGES ------ */
711 rreg_lrs_la[rreg_lrs_used].rreg = available_real_regs[j];
726 rreg = rreg_lrs_la[j].rreg;
727 vassert(!hregIsVirtual(rreg));
728 /* rreg is involved in a HLR. Record this info in the array, if
731 if (rreg_state[k].rreg == rreg)
733 vassert(k < n_rregs); /* else rreg was not found in rreg_state?! */
740 ppReg(rreg_state[j].rreg);
763 /* ------ end of FINALISE RREG LIVE RANGES ------ */
776 (*ppReg)(rreg_lrs_la[j].rreg);
783 (*ppReg)(rreg_lrs_db[j].rreg);
885 /* --------- Stage 4: establish rreg preferences --------- */
889 establish which, if any, rreg each vreg would prefer to be in.
947 (*ppReg)(rreg_lrs[j].rreg);
951 /* find the state entry for this rreg */
953 if (rreg_state[k].rreg == rreg_lrs_la[j].rreg)
956 /* and assert that this rreg is marked as unavailable */
972 if (rreg_lrs_la[k].rreg == rreg_state[j].rreg
981 /* Sanity check 3: all vreg-rreg bindings must bind registers
988 vassert(hregClass(rreg_state[j].rreg)
991 vassert(!hregIsVirtual(rreg_state[j].rreg));
1026 the dst to the src's rreg, and that's all. */
1063 /* This rreg has become associated with a different vreg and
1077 mark the associated rreg as free. */
1092 (*ppReg)(rreg_state[j].rreg);
1098 /* ------ Pre-instruction actions for fixed rreg uses ------ */
1102 one of their live ranges. If any such rreg holds a vreg, we
1103 will have to free up the rreg. The simplest solution which
1104 is correct is to spill the rreg.
1107 * Could move it into some other free rreg, if one is available
1110 of rreg HLRs that are known to be sorted by start point
1121 /* rreg_lrs_la[rreg_lrs_la_next].rreg needs to be freed up.
1132 vex_printf("need to free up rreg: ");
1133 (*ppReg)(rreg_lrs_la[rreg_lrs_la_next].rreg);
1137 if (rreg_state[k].rreg == rreg_lrs_la[rreg_lrs_la_next].rreg)
1139 /* If this fails, we don't have an entry for this rreg.
1153 (*genSpill)( &spill1, &spill2, rreg_state[k].rreg,
1186 We also build up the final vreg->rreg mapping to be applied
1276 /* Now we're trying to find a rreg for "vreg". First of all,
1277 if it already has an rreg assigned, we don't need to do
1284 addToHRegRemap(&remap, vreg, rreg_state[k].rreg);
1285 /* If this rreg is written or modified, mark it as different
1295 currently free rreg available, of the correct class. If
1297 rreg for which the next live-range event is as far ahead
1302 || hregClass(rreg_state[k].rreg) != hregClass(vreg))
1323 addToHRegRemap(&remap, vreg, rreg_state[k].rreg);
1334 (*genReload)( &reload1, &reload2, rreg_state[k].rreg,
1341 /* This rreg is read or modified by the instruction.
1369 if (hregClass(rreg_state[k].rreg) != hregClass(vreg))
1380 /* We can choose to spill any rreg satisfying
1402 vassert(hregClass(rreg_state[spillee].rreg) == hregClass(vreg));
1417 (*genSpill)( &spill1, &spill2, rreg_state[spillee].rreg,
1427 rreg. */
1443 (*genReload)( &reload1, &reload2, rreg_state[spillee].rreg,
1450 /* This rreg is read or modified by the instruction.
1462 rreg_state[spillee].rreg. Note that in the map. */
1463 addToHRegRemap(&remap, vreg, rreg_state[spillee].rreg);
1470 - a suitable vreg->rreg mapping for this instruction has been
1488 /* ------ Post-instruction actions for fixed rreg uses ------ */
1500 /* rreg_lrs_db[[rreg_lrs_db_next].rreg is exiting a hard live
1503 if (rreg_state[k].rreg == rreg_lrs_db[rreg_lrs_db_next].rreg)
1506 this rreg. Which we should. */
1533 vassert(rreg_state[j].rreg == available_real_regs[j]);
