Lines Matching refs:data_addr
362 void log_1I_1Dr_cache_access(InstrInfo* n, Addr data_addr, Word data_size)
366 // n, n->instr_addr, n->instr_len, data_addr, data_size);
371 cachesim_D1_doref(data_addr, data_size,
377 void log_1I_1Dw_cache_access(InstrInfo* n, Addr data_addr, Word data_size)
381 // n, n->instr_addr, n->instr_len, data_addr, data_size);
386 cachesim_D1_doref(data_addr, data_size,
392 void log_0I_1Dr_cache_access(InstrInfo* n, Addr data_addr, Word data_size)
395 // n, data_addr, data_size);
396 cachesim_D1_doref(data_addr, data_size,
402 void log_0I_1Dw_cache_access(InstrInfo* n, Addr data_addr, Word data_size)
405 // n, data_addr, data_size);
406 cachesim_D1_doref(data_addr, data_size,
