Lines Matching refs:Hit
41 - both blocks hit --> one hit
133 typedef enum { Hit = 0, Miss, MissDirty } CacheResult;
254 return Hit;
264 return Hit;
295 return ((res1 == Miss) || (res2 == Miss)) ? Miss : Hit;
301 return Hit;
307 if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;
308 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
315 if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;
316 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
354 return Hit;
365 return Hit;
401 return ((res1 == Miss) || (res2 == Miss)) ? Miss : Hit;
407 return Hit;
414 if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;
416 case Hit: return LL_Hit;
426 if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;
428 case Hit: return LL_Hit;
438 if ( cachesim_ref( &D1, a, size) == Hit ) {
439 /* Even for a L1 hit, the write-trough L1 passes
441 * But this causes no latency, so return the hit.
447 case Hit: return LL_Hit;
521 if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;
523 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
530 if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;
532 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
542 if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;
545 case Hit: return LL_Hit;
555 if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;
558 case Hit
569 if ( cachesim_ref( &D1, a, size) == Hit ) {
570 /* Even for a L1 hit, the write-trough L1 passes
572 * But this causes no latency, so return the hit.
578 case Hit: return LL_Hit;
719 CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
739 Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:LL miss */ \
761 CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
798 CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
901 CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
1040 case L1_Hit: return "L1 Hit ";
1041 case LL_Hit: return "LL Hit ";
