Lines Matching refs:fpRegT1
327 convertInt32ToDouble(regT1, fpRegT1);
329 emitJumpSlowToHot(branchDouble(DoubleLessThanOrEqualOrUnordered, fpRegT1, fpRegT0), target);
348 movePtrToDouble(regT1, fpRegT1);
355 emitJumpSlowToHot(branchDouble(DoubleLessThanOrEqualOrUnordered, fpRegT1, fpRegT0), target);
378 movePtrToDouble(regT1, fpRegT1);
380 emitJumpSlowToHot(branchDouble(DoubleLessThanOrEqualOrUnordered, fpRegT1, fpRegT0), target);
480 convertInt32ToDouble(regT1, fpRegT1);
482 emitJumpSlowToHot(branchDouble(DoubleLessThan, fpRegT0, fpRegT1), target);
501 movePtrToDouble(regT1, fpRegT1);
508 emitJumpSlowToHot(branchDouble(DoubleLessThan, fpRegT0, fpRegT1), target);
531 movePtrToDouble(regT1, fpRegT1);
533 emitJumpSlowToHot(branchDouble(DoubleLessThan, fpRegT0, fpRegT1), target);
634 convertInt32ToDouble(regT1, fpRegT1);
636 emitJumpSlowToHot(branchDouble(invert ? DoubleLessThanOrUnordered : DoubleGreaterThanOrEqual, fpRegT1, fpRegT0), target);
655 movePtrToDouble(regT1, fpRegT1);
662 emitJumpSlowToHot(branchDouble(invert ? DoubleLessThanOrUnordered : DoubleGreaterThanOrEqual, fpRegT1, fpRegT0), target);
685 movePtrToDouble(regT1, fpRegT1);
687 emitJumpSlowToHot(branchDouble(invert ? DoubleLessThanOrUnordered : DoubleGreaterThanOrEqual, fpRegT1, fpRegT0), target);
1003 convertInt32ToDouble(regT1, fpRegT1);
1011 convertInt32ToDouble(regT1, fpRegT1);
1022 movePtrToDouble(regT0, fpRegT1);
1031 convertInt32ToDouble(regT0, fpRegT1);
1039 addDouble(fpRegT2, fpRegT1);
1041 subDouble(fpRegT2, fpRegT1);
1043 mulDouble(fpRegT2, fpRegT1);
1046 divDouble(fpRegT2, fpRegT1);
1048 moveDoubleToPtr(fpRegT1, regT0);
1167 movePtrToDouble(regT1, fpRegT1);
1169 emitLoadInt32ToDouble(op2, fpRegT1);
1175 convertInt32ToDouble(regT1, fpRegT1);
1179 movePtrToDouble(regT1, fpRegT1);
1182 divDouble(fpRegT1, fpRegT0);
