Lines Matching full:chips
5412 on chips where it is available is controlled by \f(CW\*(C`if\-conversion2\*(C'\fR.
10417 instruction set will be used, so the code will run on all i686 family chips.
10512 Use the standard 387 floating point coprocessor present majority of chips and
10516 of other chips. See \fB\-ffloat\-store\fR for more detailed description.
10522 This instruction set is supported by Pentium3 and newer chips, in the \s-1AMD\s0 line
10523 by Athlon\-4, Athlon-xp and Athlon-mp chips. The earlier version of \s-1SSE\s0
10526 only in Pentium4 and the future \s-1AMD\s0 x86\-64 chips supports double precision
10547 amount of available registers and on chips with separate execution units for
14477 optimizes it for the Sun UltraSPARC I/II/IIi chips. With
14479 Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With
14481 Sun UltraSPARC T1 chips. With \fB\-mcpu=niagara2\fR, the compiler
14482 additionally optimizes it for Sun UltraSPARC T2 chips.
