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      1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the PPC implementation of TargetFrameLowering class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "PPCFrameLowering.h"
     15 #include "PPCInstrInfo.h"
     16 #include "PPCMachineFunctionInfo.h"
     17 #include "llvm/Function.h"
     18 #include "llvm/CodeGen/MachineFrameInfo.h"
     19 #include "llvm/CodeGen/MachineFunction.h"
     20 #include "llvm/CodeGen/MachineInstrBuilder.h"
     21 #include "llvm/CodeGen/MachineModuleInfo.h"
     22 #include "llvm/CodeGen/MachineRegisterInfo.h"
     23 #include "llvm/CodeGen/RegisterScavenging.h"
     24 #include "llvm/Target/TargetOptions.h"
     25 
     26 using namespace llvm;
     27 
     28 // FIXME This disables some code that aligns the stack to a boundary bigger than
     29 // the default (16 bytes on Darwin) when there is a stack local of greater
     30 // alignment.  This does not currently work, because the delta between old and
     31 // new stack pointers is added to offsets that reference incoming parameters
     32 // after the prolog is generated, and the code that does that doesn't handle a
     33 // variable delta.  You don't want to do that anyway; a better approach is to
     34 // reserve another register that retains to the incoming stack pointer, and
     35 // reference parameters relative to that.
     36 #define ALIGN_STACK 0
     37 
     38 
     39 /// VRRegNo - Map from a numbered VR register to its enum value.
     40 ///
     41 static const uint16_t VRRegNo[] = {
     42  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
     43  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
     44  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
     45  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
     46 };
     47 
     48 /// RemoveVRSaveCode - We have found that this function does not need any code
     49 /// to manipulate the VRSAVE register, even though it uses vector registers.
     50 /// This can happen when the only registers used are known to be live in or out
     51 /// of the function.  Remove all of the VRSAVE related code from the function.
     52 static void RemoveVRSaveCode(MachineInstr *MI) {
     53   MachineBasicBlock *Entry = MI->getParent();
     54   MachineFunction *MF = Entry->getParent();
     55 
     56   // We know that the MTVRSAVE instruction immediately follows MI.  Remove it.
     57   MachineBasicBlock::iterator MBBI = MI;
     58   ++MBBI;
     59   assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
     60   MBBI->eraseFromParent();
     61 
     62   bool RemovedAllMTVRSAVEs = true;
     63   // See if we can find and remove the MTVRSAVE instruction from all of the
     64   // epilog blocks.
     65   for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
     66     // If last instruction is a return instruction, add an epilogue
     67     if (!I->empty() && I->back().isReturn()) {
     68       bool FoundIt = false;
     69       for (MBBI = I->end(); MBBI != I->begin(); ) {
     70         --MBBI;
     71         if (MBBI->getOpcode() == PPC::MTVRSAVE) {
     72           MBBI->eraseFromParent();  // remove it.
     73           FoundIt = true;
     74           break;
     75         }
     76       }
     77       RemovedAllMTVRSAVEs &= FoundIt;
     78     }
     79   }
     80 
     81   // If we found and removed all MTVRSAVE instructions, remove the read of
     82   // VRSAVE as well.
     83   if (RemovedAllMTVRSAVEs) {
     84     MBBI = MI;
     85     assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
     86     --MBBI;
     87     assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
     88     MBBI->eraseFromParent();
     89   }
     90 
     91   // Finally, nuke the UPDATE_VRSAVE.
     92   MI->eraseFromParent();
     93 }
     94 
     95 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
     96 // instruction selector.  Based on the vector registers that have been used,
     97 // transform this into the appropriate ORI instruction.
     98 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
     99   MachineFunction *MF = MI->getParent()->getParent();
    100   DebugLoc dl = MI->getDebugLoc();
    101 
    102   unsigned UsedRegMask = 0;
    103   for (unsigned i = 0; i != 32; ++i)
    104     if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
    105       UsedRegMask |= 1 << (31-i);
    106 
    107   // Live in and live out values already must be in the mask, so don't bother
    108   // marking them.
    109   for (MachineRegisterInfo::livein_iterator
    110        I = MF->getRegInfo().livein_begin(),
    111        E = MF->getRegInfo().livein_end(); I != E; ++I) {
    112     unsigned RegNo = getPPCRegisterNumbering(I->first);
    113     if (VRRegNo[RegNo] == I->first)        // If this really is a vector reg.
    114       UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
    115   }
    116   for (MachineRegisterInfo::liveout_iterator
    117        I = MF->getRegInfo().liveout_begin(),
    118        E = MF->getRegInfo().liveout_end(); I != E; ++I) {
    119     unsigned RegNo = getPPCRegisterNumbering(*I);
    120     if (VRRegNo[RegNo] == *I)              // If this really is a vector reg.
    121       UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
    122   }
    123 
    124   // If no registers are used, turn this into a copy.
    125   if (UsedRegMask == 0) {
    126     // Remove all VRSAVE code.
    127     RemoveVRSaveCode(MI);
    128     return;
    129   }
    130 
    131   unsigned SrcReg = MI->getOperand(1).getReg();
    132   unsigned DstReg = MI->getOperand(0).getReg();
    133 
    134   if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
    135     if (DstReg != SrcReg)
    136       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
    137         .addReg(SrcReg)
    138         .addImm(UsedRegMask);
    139     else
    140       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
    141         .addReg(SrcReg, RegState::Kill)
    142         .addImm(UsedRegMask);
    143   } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
    144     if (DstReg != SrcReg)
    145       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
    146         .addReg(SrcReg)
    147         .addImm(UsedRegMask >> 16);
    148     else
    149       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
    150         .addReg(SrcReg, RegState::Kill)
    151         .addImm(UsedRegMask >> 16);
    152   } else {
    153     if (DstReg != SrcReg)
    154       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
    155         .addReg(SrcReg)
    156         .addImm(UsedRegMask >> 16);
    157     else
    158       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
    159         .addReg(SrcReg, RegState::Kill)
    160         .addImm(UsedRegMask >> 16);
    161 
    162     BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
    163       .addReg(DstReg, RegState::Kill)
    164       .addImm(UsedRegMask & 0xFFFF);
    165   }
    166 
    167   // Remove the old UPDATE_VRSAVE instruction.
    168   MI->eraseFromParent();
    169 }
    170 
    171 /// determineFrameLayout - Determine the size of the frame and maximum call
    172 /// frame size.
    173 void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const {
    174   MachineFrameInfo *MFI = MF.getFrameInfo();
    175 
    176   // Get the number of bytes to allocate from the FrameInfo
    177   unsigned FrameSize = MFI->getStackSize();
    178 
    179   // Get the alignments provided by the target, and the maximum alignment
    180   // (if any) of the fixed frame objects.
    181   unsigned MaxAlign = MFI->getMaxAlignment();
    182   unsigned TargetAlign = getStackAlignment();
    183   unsigned AlignMask = TargetAlign - 1;  //
    184 
    185   // If we are a leaf function, and use up to 224 bytes of stack space,
    186   // don't have a frame pointer, calls, or dynamic alloca then we do not need
    187   // to adjust the stack pointer (we fit in the Red Zone).
    188   bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
    189   // FIXME SVR4 The 32-bit SVR4 ABI has no red zone.
    190   if (!DisableRedZone &&
    191       FrameSize <= 224 &&                          // Fits in red zone.
    192       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
    193       !MFI->adjustsStack() &&                      // No calls.
    194       (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
    195     // No need for frame
    196     MFI->setStackSize(0);
    197     return;
    198   }
    199 
    200   // Get the maximum call frame size of all the calls.
    201   unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
    202 
    203   // Maximum call frame needs to be at least big enough for linkage and 8 args.
    204   unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
    205                                                   Subtarget.isDarwinABI());
    206   maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
    207 
    208   // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
    209   // that allocations will be aligned.
    210   if (MFI->hasVarSizedObjects())
    211     maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
    212 
    213   // Update maximum call frame size.
    214   MFI->setMaxCallFrameSize(maxCallFrameSize);
    215 
    216   // Include call frame size in total.
    217   FrameSize += maxCallFrameSize;
    218 
    219   // Make sure the frame is aligned.
    220   FrameSize = (FrameSize + AlignMask) & ~AlignMask;
    221 
    222   // Update frame info.
    223   MFI->setStackSize(FrameSize);
    224 }
    225 
    226 // hasFP - Return true if the specified function actually has a dedicated frame
    227 // pointer register.
    228 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
    229   const MachineFrameInfo *MFI = MF.getFrameInfo();
    230   // FIXME: This is pretty much broken by design: hasFP() might be called really
    231   // early, before the stack layout was calculated and thus hasFP() might return
    232   // true or false here depending on the time of call.
    233   return (MFI->getStackSize()) && needsFP(MF);
    234 }
    235 
    236 // needsFP - Return true if the specified function should have a dedicated frame
    237 // pointer register.  This is true if the function has variable sized allocas or
    238 // if frame pointer elimination is disabled.
    239 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
    240   const MachineFrameInfo *MFI = MF.getFrameInfo();
    241 
    242   // Naked functions have no stack frame pushed, so we don't have a frame
    243   // pointer.
    244   if (MF.getFunction()->hasFnAttr(Attribute::Naked))
    245     return false;
    246 
    247   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
    248     MFI->hasVarSizedObjects() ||
    249     (MF.getTarget().Options.GuaranteedTailCallOpt &&
    250      MF.getInfo<PPCFunctionInfo>()->hasFastCall());
    251 }
    252 
    253 
    254 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
    255   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
    256   MachineBasicBlock::iterator MBBI = MBB.begin();
    257   MachineFrameInfo *MFI = MF.getFrameInfo();
    258   const PPCInstrInfo &TII =
    259     *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
    260 
    261   MachineModuleInfo &MMI = MF.getMMI();
    262   DebugLoc dl;
    263   bool needsFrameMoves = MMI.hasDebugInfo() ||
    264     MF.getFunction()->needsUnwindTableEntry();
    265 
    266   // Prepare for frame info.
    267   MCSymbol *FrameLabel = 0;
    268 
    269   // Scan the prolog, looking for an UPDATE_VRSAVE instruction.  If we find it,
    270   // process it.
    271   for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
    272     if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
    273       HandleVRSaveUpdate(MBBI, TII);
    274       break;
    275     }
    276   }
    277 
    278   // Move MBBI back to the beginning of the function.
    279   MBBI = MBB.begin();
    280 
    281   // Work out frame sizes.
    282   // FIXME: determineFrameLayout() may change the frame size. This should be
    283   // moved upper, to some hook.
    284   determineFrameLayout(MF);
    285   unsigned FrameSize = MFI->getStackSize();
    286 
    287   int NegFrameSize = -FrameSize;
    288 
    289   // Get processor type.
    290   bool isPPC64 = Subtarget.isPPC64();
    291   // Get operating system
    292   bool isDarwinABI = Subtarget.isDarwinABI();
    293   // Check if the link register (LR) must be saved.
    294   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
    295   bool MustSaveLR = FI->mustSaveLR();
    296   // Do we have a frame pointer for this function?
    297   bool HasFP = hasFP(MF);
    298 
    299   int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
    300 
    301   int FPOffset = 0;
    302   if (HasFP) {
    303     if (Subtarget.isSVR4ABI()) {
    304       MachineFrameInfo *FFI = MF.getFrameInfo();
    305       int FPIndex = FI->getFramePointerSaveIndex();
    306       assert(FPIndex && "No Frame Pointer Save Slot!");
    307       FPOffset = FFI->getObjectOffset(FPIndex);
    308     } else {
    309       FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
    310     }
    311   }
    312 
    313   if (isPPC64) {
    314     if (MustSaveLR)
    315       BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
    316 
    317     if (HasFP)
    318       BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
    319         .addReg(PPC::X31)
    320         .addImm(FPOffset/4)
    321         .addReg(PPC::X1);
    322 
    323     if (MustSaveLR)
    324       BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
    325         .addReg(PPC::X0)
    326         .addImm(LROffset / 4)
    327         .addReg(PPC::X1);
    328   } else {
    329     if (MustSaveLR)
    330       BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
    331 
    332     if (HasFP)
    333       BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
    334         .addReg(PPC::R31)
    335         .addImm(FPOffset)
    336         .addReg(PPC::R1);
    337 
    338     if (MustSaveLR)
    339       BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
    340         .addReg(PPC::R0)
    341         .addImm(LROffset)
    342         .addReg(PPC::R1);
    343   }
    344 
    345   // Skip if a leaf routine.
    346   if (!FrameSize) return;
    347 
    348   // Get stack alignments.
    349   unsigned TargetAlign = getStackAlignment();
    350   unsigned MaxAlign = MFI->getMaxAlignment();
    351 
    352   // Adjust stack pointer: r1 += NegFrameSize.
    353   // If there is a preferred stack alignment, align R1 now
    354   if (!isPPC64) {
    355     // PPC32.
    356     if (ALIGN_STACK && MaxAlign > TargetAlign) {
    357       assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
    358              "Invalid alignment!");
    359       assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
    360 
    361       BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
    362         .addReg(PPC::R1)
    363         .addImm(0)
    364         .addImm(32 - Log2_32(MaxAlign))
    365         .addImm(31);
    366       BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
    367         .addReg(PPC::R0, RegState::Kill)
    368         .addImm(NegFrameSize);
    369       BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
    370         .addReg(PPC::R1, RegState::Kill)
    371         .addReg(PPC::R1, RegState::Define)
    372         .addReg(PPC::R0);
    373     } else if (isInt<16>(NegFrameSize)) {
    374       BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
    375         .addReg(PPC::R1)
    376         .addImm(NegFrameSize)
    377         .addReg(PPC::R1);
    378     } else {
    379       BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
    380         .addImm(NegFrameSize >> 16);
    381       BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
    382         .addReg(PPC::R0, RegState::Kill)
    383         .addImm(NegFrameSize & 0xFFFF);
    384       BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
    385         .addReg(PPC::R1, RegState::Kill)
    386         .addReg(PPC::R1, RegState::Define)
    387         .addReg(PPC::R0);
    388     }
    389   } else {    // PPC64.
    390     if (ALIGN_STACK && MaxAlign > TargetAlign) {
    391       assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
    392              "Invalid alignment!");
    393       assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
    394 
    395       BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
    396         .addReg(PPC::X1)
    397         .addImm(0)
    398         .addImm(64 - Log2_32(MaxAlign));
    399       BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
    400         .addReg(PPC::X0)
    401         .addImm(NegFrameSize);
    402       BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
    403         .addReg(PPC::X1, RegState::Kill)
    404         .addReg(PPC::X1, RegState::Define)
    405         .addReg(PPC::X0);
    406     } else if (isInt<16>(NegFrameSize)) {
    407       BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
    408         .addReg(PPC::X1)
    409         .addImm(NegFrameSize / 4)
    410         .addReg(PPC::X1);
    411     } else {
    412       BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
    413         .addImm(NegFrameSize >> 16);
    414       BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
    415         .addReg(PPC::X0, RegState::Kill)
    416         .addImm(NegFrameSize & 0xFFFF);
    417       BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
    418         .addReg(PPC::X1, RegState::Kill)
    419         .addReg(PPC::X1, RegState::Define)
    420         .addReg(PPC::X0);
    421     }
    422   }
    423 
    424   std::vector<MachineMove> &Moves = MMI.getFrameMoves();
    425 
    426   // Add the "machine moves" for the instructions we generated above, but in
    427   // reverse order.
    428   if (needsFrameMoves) {
    429     // Mark effective beginning of when frame pointer becomes valid.
    430     FrameLabel = MMI.getContext().CreateTempSymbol();
    431     BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
    432 
    433     // Show update of SP.
    434     if (NegFrameSize) {
    435       MachineLocation SPDst(MachineLocation::VirtualFP);
    436       MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
    437       Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
    438     } else {
    439       MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
    440       Moves.push_back(MachineMove(FrameLabel, SP, SP));
    441     }
    442 
    443     if (HasFP) {
    444       MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
    445       MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
    446       Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
    447     }
    448 
    449     if (MustSaveLR) {
    450       MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
    451       MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
    452       Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc));
    453     }
    454   }
    455 
    456   MCSymbol *ReadyLabel = 0;
    457 
    458   // If there is a frame pointer, copy R1 into R31
    459   if (HasFP) {
    460     if (!isPPC64) {
    461       BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
    462         .addReg(PPC::R1)
    463         .addReg(PPC::R1);
    464     } else {
    465       BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
    466         .addReg(PPC::X1)
    467         .addReg(PPC::X1);
    468     }
    469 
    470     if (needsFrameMoves) {
    471       ReadyLabel = MMI.getContext().CreateTempSymbol();
    472 
    473       // Mark effective beginning of when frame pointer is ready.
    474       BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
    475 
    476       MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
    477                                     (isPPC64 ? PPC::X1 : PPC::R1));
    478       MachineLocation FPSrc(MachineLocation::VirtualFP);
    479       Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
    480     }
    481   }
    482 
    483   if (needsFrameMoves) {
    484     MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
    485 
    486     // Add callee saved registers to move list.
    487     const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
    488     for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
    489       int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
    490       unsigned Reg = CSI[I].getReg();
    491       if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
    492 
    493       // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
    494       // subregisters of CR2. We just need to emit a move of CR2.
    495       if (PPC::CRBITRCRegisterClass->contains(Reg))
    496         continue;
    497 
    498       MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
    499       MachineLocation CSSrc(Reg);
    500       Moves.push_back(MachineMove(Label, CSDst, CSSrc));
    501     }
    502   }
    503 }
    504 
    505 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
    506                                 MachineBasicBlock &MBB) const {
    507   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
    508   assert(MBBI != MBB.end() && "Returning block has no terminator");
    509   const PPCInstrInfo &TII =
    510     *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
    511 
    512   unsigned RetOpcode = MBBI->getOpcode();
    513   DebugLoc dl;
    514 
    515   assert((RetOpcode == PPC::BLR ||
    516           RetOpcode == PPC::TCRETURNri ||
    517           RetOpcode == PPC::TCRETURNdi ||
    518           RetOpcode == PPC::TCRETURNai ||
    519           RetOpcode == PPC::TCRETURNri8 ||
    520           RetOpcode == PPC::TCRETURNdi8 ||
    521           RetOpcode == PPC::TCRETURNai8) &&
    522          "Can only insert epilog into returning blocks");
    523 
    524   // Get alignment info so we know how to restore r1
    525   const MachineFrameInfo *MFI = MF.getFrameInfo();
    526   unsigned TargetAlign = getStackAlignment();
    527   unsigned MaxAlign = MFI->getMaxAlignment();
    528 
    529   // Get the number of bytes allocated from the FrameInfo.
    530   int FrameSize = MFI->getStackSize();
    531 
    532   // Get processor type.
    533   bool isPPC64 = Subtarget.isPPC64();
    534   // Get operating system
    535   bool isDarwinABI = Subtarget.isDarwinABI();
    536   // Check if the link register (LR) has been saved.
    537   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
    538   bool MustSaveLR = FI->mustSaveLR();
    539   // Do we have a frame pointer for this function?
    540   bool HasFP = hasFP(MF);
    541 
    542   int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
    543 
    544   int FPOffset = 0;
    545   if (HasFP) {
    546     if (Subtarget.isSVR4ABI()) {
    547       MachineFrameInfo *FFI = MF.getFrameInfo();
    548       int FPIndex = FI->getFramePointerSaveIndex();
    549       assert(FPIndex && "No Frame Pointer Save Slot!");
    550       FPOffset = FFI->getObjectOffset(FPIndex);
    551     } else {
    552       FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
    553     }
    554   }
    555 
    556   bool UsesTCRet =  RetOpcode == PPC::TCRETURNri ||
    557     RetOpcode == PPC::TCRETURNdi ||
    558     RetOpcode == PPC::TCRETURNai ||
    559     RetOpcode == PPC::TCRETURNri8 ||
    560     RetOpcode == PPC::TCRETURNdi8 ||
    561     RetOpcode == PPC::TCRETURNai8;
    562 
    563   if (UsesTCRet) {
    564     int MaxTCRetDelta = FI->getTailCallSPDelta();
    565     MachineOperand &StackAdjust = MBBI->getOperand(1);
    566     assert(StackAdjust.isImm() && "Expecting immediate value.");
    567     // Adjust stack pointer.
    568     int StackAdj = StackAdjust.getImm();
    569     int Delta = StackAdj - MaxTCRetDelta;
    570     assert((Delta >= 0) && "Delta must be positive");
    571     if (MaxTCRetDelta>0)
    572       FrameSize += (StackAdj +Delta);
    573     else
    574       FrameSize += StackAdj;
    575   }
    576 
    577   if (FrameSize) {
    578     // The loaded (or persistent) stack pointer value is offset by the 'stwu'
    579     // on entry to the function.  Add this offset back now.
    580     if (!isPPC64) {
    581       // If this function contained a fastcc call and GuaranteedTailCallOpt is
    582       // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
    583       // call which invalidates the stack pointer value in SP(0). So we use the
    584       // value of R31 in this case.
    585       if (FI->hasFastCall() && isInt<16>(FrameSize)) {
    586         assert(hasFP(MF) && "Expecting a valid the frame pointer.");
    587         BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
    588           .addReg(PPC::R31).addImm(FrameSize);
    589       } else if(FI->hasFastCall()) {
    590         BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
    591           .addImm(FrameSize >> 16);
    592         BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
    593           .addReg(PPC::R0, RegState::Kill)
    594           .addImm(FrameSize & 0xFFFF);
    595         BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
    596           .addReg(PPC::R1)
    597           .addReg(PPC::R31)
    598           .addReg(PPC::R0);
    599       } else if (isInt<16>(FrameSize) &&
    600                  (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
    601                  !MFI->hasVarSizedObjects()) {
    602         BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
    603           .addReg(PPC::R1).addImm(FrameSize);
    604       } else {
    605         BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
    606           .addImm(0).addReg(PPC::R1);
    607       }
    608     } else {
    609       if (FI->hasFastCall() && isInt<16>(FrameSize)) {
    610         assert(hasFP(MF) && "Expecting a valid the frame pointer.");
    611         BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
    612           .addReg(PPC::X31).addImm(FrameSize);
    613       } else if(FI->hasFastCall()) {
    614         BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
    615           .addImm(FrameSize >> 16);
    616         BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
    617           .addReg(PPC::X0, RegState::Kill)
    618           .addImm(FrameSize & 0xFFFF);
    619         BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
    620           .addReg(PPC::X1)
    621           .addReg(PPC::X31)
    622           .addReg(PPC::X0);
    623       } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
    624             !MFI->hasVarSizedObjects()) {
    625         BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
    626            .addReg(PPC::X1).addImm(FrameSize);
    627       } else {
    628         BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
    629            .addImm(0).addReg(PPC::X1);
    630       }
    631     }
    632   }
    633 
    634   if (isPPC64) {
    635     if (MustSaveLR)
    636       BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
    637         .addImm(LROffset/4).addReg(PPC::X1);
    638 
    639     if (HasFP)
    640       BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
    641         .addImm(FPOffset/4).addReg(PPC::X1);
    642 
    643     if (MustSaveLR)
    644       BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
    645   } else {
    646     if (MustSaveLR)
    647       BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
    648           .addImm(LROffset).addReg(PPC::R1);
    649 
    650     if (HasFP)
    651       BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
    652           .addImm(FPOffset).addReg(PPC::R1);
    653 
    654     if (MustSaveLR)
    655       BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
    656   }
    657 
    658   // Callee pop calling convention. Pop parameter/linkage area. Used for tail
    659   // call optimization
    660   if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
    661       MF.getFunction()->getCallingConv() == CallingConv::Fast) {
    662      PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
    663      unsigned CallerAllocatedAmt = FI->getMinReservedArea();
    664      unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
    665      unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
    666      unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
    667      unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
    668      unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
    669      unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
    670      unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
    671 
    672      if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
    673        BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
    674          .addReg(StackReg).addImm(CallerAllocatedAmt);
    675      } else {
    676        BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
    677           .addImm(CallerAllocatedAmt >> 16);
    678        BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
    679           .addReg(TmpReg, RegState::Kill)
    680           .addImm(CallerAllocatedAmt & 0xFFFF);
    681        BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
    682           .addReg(StackReg)
    683           .addReg(FPReg)
    684           .addReg(TmpReg);
    685      }
    686   } else if (RetOpcode == PPC::TCRETURNdi) {
    687     MBBI = MBB.getLastNonDebugInstr();
    688     MachineOperand &JumpTarget = MBBI->getOperand(0);
    689     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
    690       addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
    691   } else if (RetOpcode == PPC::TCRETURNri) {
    692     MBBI = MBB.getLastNonDebugInstr();
    693     assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
    694     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
    695   } else if (RetOpcode == PPC::TCRETURNai) {
    696     MBBI = MBB.getLastNonDebugInstr();
    697     MachineOperand &JumpTarget = MBBI->getOperand(0);
    698     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
    699   } else if (RetOpcode == PPC::TCRETURNdi8) {
    700     MBBI = MBB.getLastNonDebugInstr();
    701     MachineOperand &JumpTarget = MBBI->getOperand(0);
    702     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
    703       addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
    704   } else if (RetOpcode == PPC::TCRETURNri8) {
    705     MBBI = MBB.getLastNonDebugInstr();
    706     assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
    707     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
    708   } else if (RetOpcode == PPC::TCRETURNai8) {
    709     MBBI = MBB.getLastNonDebugInstr();
    710     MachineOperand &JumpTarget = MBBI->getOperand(0);
    711     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
    712   }
    713 }
    714 
    715 static bool spillsCR(const MachineFunction &MF) {
    716   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
    717   return FuncInfo->isCRSpilled();
    718 }
    719 
    720 /// MustSaveLR - Return true if this function requires that we save the LR
    721 /// register onto the stack in the prolog and restore it in the epilog of the
    722 /// function.
    723 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
    724   const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
    725 
    726   // We need a save/restore of LR if there is any def of LR (which is
    727   // defined by calls, including the PIC setup sequence), or if there is
    728   // some use of the LR stack slot (e.g. for builtin_return_address).
    729   // (LR comes in 32 and 64 bit versions.)
    730   MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
    731   return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
    732 }
    733 
    734 void
    735 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
    736                                                    RegScavenger *RS) const {
    737   const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
    738 
    739   //  Save and clear the LR state.
    740   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
    741   unsigned LR = RegInfo->getRARegister();
    742   FI->setMustSaveLR(MustSaveLR(MF, LR));
    743   MF.getRegInfo().setPhysRegUnused(LR);
    744 
    745   //  Save R31 if necessary
    746   int FPSI = FI->getFramePointerSaveIndex();
    747   bool isPPC64 = Subtarget.isPPC64();
    748   bool isDarwinABI  = Subtarget.isDarwinABI();
    749   MachineFrameInfo *MFI = MF.getFrameInfo();
    750 
    751   // If the frame pointer save index hasn't been defined yet.
    752   if (!FPSI && needsFP(MF)) {
    753     // Find out what the fix offset of the frame pointer save area.
    754     int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
    755     // Allocate the frame index for frame pointer save area.
    756     FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
    757     // Save the result.
    758     FI->setFramePointerSaveIndex(FPSI);
    759   }
    760 
    761   // Reserve stack space to move the linkage area to in case of a tail call.
    762   int TCSPDelta = 0;
    763   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
    764       (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
    765     MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
    766   }
    767 
    768   // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
    769   // a large stack, which will require scavenging a register to materialize a
    770   // large offset.
    771   // FIXME: this doesn't actually check stack size, so is a bit pessimistic
    772   // FIXME: doesn't detect whether or not we need to spill vXX, which requires
    773   //        r0 for now.
    774 
    775   if (RegInfo->requiresRegisterScavenging(MF))
    776     if (needsFP(MF) || spillsCR(MF)) {
    777       const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
    778       const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
    779       const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
    780       RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
    781                                                          RC->getAlignment(),
    782                                                          false));
    783     }
    784 }
    785 
    786 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF)
    787                                                                         const {
    788   // Early exit if not using the SVR4 ABI.
    789   if (!Subtarget.isSVR4ABI())
    790     return;
    791 
    792   // Get callee saved register information.
    793   MachineFrameInfo *FFI = MF.getFrameInfo();
    794   const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
    795 
    796   // Early exit if no callee saved registers are modified!
    797   if (CSI.empty() && !needsFP(MF)) {
    798     return;
    799   }
    800 
    801   unsigned MinGPR = PPC::R31;
    802   unsigned MinG8R = PPC::X31;
    803   unsigned MinFPR = PPC::F31;
    804   unsigned MinVR = PPC::V31;
    805 
    806   bool HasGPSaveArea = false;
    807   bool HasG8SaveArea = false;
    808   bool HasFPSaveArea = false;
    809   bool HasCRSaveArea = false;
    810   bool HasVRSAVESaveArea = false;
    811   bool HasVRSaveArea = false;
    812 
    813   SmallVector<CalleeSavedInfo, 18> GPRegs;
    814   SmallVector<CalleeSavedInfo, 18> G8Regs;
    815   SmallVector<CalleeSavedInfo, 18> FPRegs;
    816   SmallVector<CalleeSavedInfo, 18> VRegs;
    817 
    818   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
    819     unsigned Reg = CSI[i].getReg();
    820     if (PPC::GPRCRegisterClass->contains(Reg)) {
    821       HasGPSaveArea = true;
    822 
    823       GPRegs.push_back(CSI[i]);
    824 
    825       if (Reg < MinGPR) {
    826         MinGPR = Reg;
    827       }
    828     } else if (PPC::G8RCRegisterClass->contains(Reg)) {
    829       HasG8SaveArea = true;
    830 
    831       G8Regs.push_back(CSI[i]);
    832 
    833       if (Reg < MinG8R) {
    834         MinG8R = Reg;
    835       }
    836     } else if (PPC::F8RCRegisterClass->contains(Reg)) {
    837       HasFPSaveArea = true;
    838 
    839       FPRegs.push_back(CSI[i]);
    840 
    841       if (Reg < MinFPR) {
    842         MinFPR = Reg;
    843       }
    844 // FIXME SVR4: Disable CR save area for now.
    845     } else if (PPC::CRBITRCRegisterClass->contains(Reg)
    846                || PPC::CRRCRegisterClass->contains(Reg)) {
    847 //      HasCRSaveArea = true;
    848     } else if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
    849       HasVRSAVESaveArea = true;
    850     } else if (PPC::VRRCRegisterClass->contains(Reg)) {
    851       HasVRSaveArea = true;
    852 
    853       VRegs.push_back(CSI[i]);
    854 
    855       if (Reg < MinVR) {
    856         MinVR = Reg;
    857       }
    858     } else {
    859       llvm_unreachable("Unknown RegisterClass!");
    860     }
    861   }
    862 
    863   PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
    864 
    865   int64_t LowerBound = 0;
    866 
    867   // Take into account stack space reserved for tail calls.
    868   int TCSPDelta = 0;
    869   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
    870       (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
    871     LowerBound = TCSPDelta;
    872   }
    873 
    874   // The Floating-point register save area is right below the back chain word
    875   // of the previous stack frame.
    876   if (HasFPSaveArea) {
    877     for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
    878       int FI = FPRegs[i].getFrameIdx();
    879 
    880       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
    881     }
    882 
    883     LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8;
    884   }
    885 
    886   // Check whether the frame pointer register is allocated. If so, make sure it
    887   // is spilled to the correct offset.
    888   if (needsFP(MF)) {
    889     HasGPSaveArea = true;
    890 
    891     int FI = PFI->getFramePointerSaveIndex();
    892     assert(FI && "No Frame Pointer Save Slot!");
    893 
    894     FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
    895   }
    896 
    897   // General register save area starts right below the Floating-point
    898   // register save area.
    899   if (HasGPSaveArea || HasG8SaveArea) {
    900     // Move general register save area spill slots down, taking into account
    901     // the size of the Floating-point register save area.
    902     for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
    903       int FI = GPRegs[i].getFrameIdx();
    904 
    905       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
    906     }
    907 
    908     // Move general register save area spill slots down, taking into account
    909     // the size of the Floating-point register save area.
    910     for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
    911       int FI = G8Regs[i].getFrameIdx();
    912 
    913       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
    914     }
    915 
    916     unsigned MinReg =
    917       std::min<unsigned>(getPPCRegisterNumbering(MinGPR),
    918                          getPPCRegisterNumbering(MinG8R));
    919 
    920     if (Subtarget.isPPC64()) {
    921       LowerBound -= (31 - MinReg + 1) * 8;
    922     } else {
    923       LowerBound -= (31 - MinReg + 1) * 4;
    924     }
    925   }
    926 
    927   // The CR save area is below the general register save area.
    928   if (HasCRSaveArea) {
    929     // FIXME SVR4: Is it actually possible to have multiple elements in CSI
    930     //             which have the CR/CRBIT register class?
    931     // Adjust the frame index of the CR spill slot.
    932     for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
    933       unsigned Reg = CSI[i].getReg();
    934 
    935       if (PPC::CRBITRCRegisterClass->contains(Reg) ||
    936           PPC::CRRCRegisterClass->contains(Reg)) {
    937         int FI = CSI[i].getFrameIdx();
    938 
    939         FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
    940       }
    941     }
    942 
    943     LowerBound -= 4; // The CR save area is always 4 bytes long.
    944   }
    945 
    946   if (HasVRSAVESaveArea) {
    947     // FIXME SVR4: Is it actually possible to have multiple elements in CSI
    948     //             which have the VRSAVE register class?
    949     // Adjust the frame index of the VRSAVE spill slot.
    950     for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
    951       unsigned Reg = CSI[i].getReg();
    952 
    953       if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
    954         int FI = CSI[i].getFrameIdx();
    955 
    956         FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
    957       }
    958     }
    959 
    960     LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
    961   }
    962 
    963   if (HasVRSaveArea) {
    964     // Insert alignment padding, we need 16-byte alignment.
    965     LowerBound = (LowerBound - 15) & ~(15);
    966 
    967     for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
    968       int FI = VRegs[i].getFrameIdx();
    969 
    970       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
    971     }
    972   }
    973 }
    974