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      1 
      2 /*---------------------------------------------------------------*/
      3 /*--- begin                                   host_x86_defs.h ---*/
      4 /*---------------------------------------------------------------*/
      5 
      6 /*
      7    This file is part of Valgrind, a dynamic binary instrumentation
      8    framework.
      9 
     10    Copyright (C) 2004-2011 OpenWorks LLP
     11       info (at) open-works.net
     12 
     13    This program is free software; you can redistribute it and/or
     14    modify it under the terms of the GNU General Public License as
     15    published by the Free Software Foundation; either version 2 of the
     16    License, or (at your option) any later version.
     17 
     18    This program is distributed in the hope that it will be useful, but
     19    WITHOUT ANY WARRANTY; without even the implied warranty of
     20    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     21    General Public License for more details.
     22 
     23    You should have received a copy of the GNU General Public License
     24    along with this program; if not, write to the Free Software
     25    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
     26    02110-1301, USA.
     27 
     28    The GNU General Public License is contained in the file COPYING.
     29 
     30    Neither the names of the U.S. Department of Energy nor the
     31    University of California nor the names of its contributors may be
     32    used to endorse or promote products derived from this software
     33    without prior written permission.
     34 */
     35 
     36 #ifndef __VEX_HOST_X86_DEFS_H
     37 #define __VEX_HOST_X86_DEFS_H
     38 
     39 
     40 /* --------- Registers. --------- */
     41 
     42 /* The usual HReg abstraction.  There are 8 real int regs,
     43    6 real float regs, and 8 real vector regs.
     44 */
     45 
     46 extern void ppHRegX86 ( HReg );
     47 
     48 extern HReg hregX86_EAX ( void );
     49 extern HReg hregX86_EBX ( void );
     50 extern HReg hregX86_ECX ( void );
     51 extern HReg hregX86_EDX ( void );
     52 extern HReg hregX86_ESP ( void );
     53 extern HReg hregX86_EBP ( void );
     54 extern HReg hregX86_ESI ( void );
     55 extern HReg hregX86_EDI ( void );
     56 
     57 extern HReg hregX86_FAKE0 ( void );
     58 extern HReg hregX86_FAKE1 ( void );
     59 extern HReg hregX86_FAKE2 ( void );
     60 extern HReg hregX86_FAKE3 ( void );
     61 extern HReg hregX86_FAKE4 ( void );
     62 extern HReg hregX86_FAKE5 ( void );
     63 
     64 extern HReg hregX86_XMM0 ( void );
     65 extern HReg hregX86_XMM1 ( void );
     66 extern HReg hregX86_XMM2 ( void );
     67 extern HReg hregX86_XMM3 ( void );
     68 extern HReg hregX86_XMM4 ( void );
     69 extern HReg hregX86_XMM5 ( void );
     70 extern HReg hregX86_XMM6 ( void );
     71 extern HReg hregX86_XMM7 ( void );
     72 
     73 
     74 /* --------- Condition codes, Intel encoding. --------- */
     75 
     76 typedef
     77    enum {
     78       Xcc_O      = 0,  /* overflow           */
     79       Xcc_NO     = 1,  /* no overflow        */
     80 
     81       Xcc_B      = 2,  /* below              */
     82       Xcc_NB     = 3,  /* not below          */
     83 
     84       Xcc_Z      = 4,  /* zero               */
     85       Xcc_NZ     = 5,  /* not zero           */
     86 
     87       Xcc_BE     = 6,  /* below or equal     */
     88       Xcc_NBE    = 7,  /* not below or equal */
     89 
     90       Xcc_S      = 8,  /* negative           */
     91       Xcc_NS     = 9,  /* not negative       */
     92 
     93       Xcc_P      = 10, /* parity even        */
     94       Xcc_NP     = 11, /* not parity even    */
     95 
     96       Xcc_L      = 12, /* jump less          */
     97       Xcc_NL     = 13, /* not less           */
     98 
     99       Xcc_LE     = 14, /* less or equal      */
    100       Xcc_NLE    = 15, /* not less or equal  */
    101 
    102       Xcc_ALWAYS = 16  /* the usual hack     */
    103    }
    104    X86CondCode;
    105 
    106 extern HChar* showX86CondCode ( X86CondCode );
    107 
    108 
    109 /* --------- Memory address expressions (amodes). --------- */
    110 
    111 typedef
    112    enum {
    113      Xam_IR,        /* Immediate + Reg */
    114      Xam_IRRS       /* Immediate + Reg1 + (Reg2 << Shift) */
    115    }
    116    X86AModeTag;
    117 
    118 typedef
    119    struct {
    120       X86AModeTag tag;
    121       union {
    122          struct {
    123             UInt imm;
    124             HReg reg;
    125          } IR;
    126          struct {
    127             UInt imm;
    128             HReg base;
    129             HReg index;
    130             Int  shift; /* 0, 1, 2 or 3 only */
    131          } IRRS;
    132       } Xam;
    133    }
    134    X86AMode;
    135 
    136 extern X86AMode* X86AMode_IR   ( UInt, HReg );
    137 extern X86AMode* X86AMode_IRRS ( UInt, HReg, HReg, Int );
    138 
    139 extern X86AMode* dopyX86AMode ( X86AMode* );
    140 
    141 extern void ppX86AMode ( X86AMode* );
    142 
    143 
    144 /* --------- Operand, which can be reg, immediate or memory. --------- */
    145 
    146 typedef
    147    enum {
    148       Xrmi_Imm,
    149       Xrmi_Reg,
    150       Xrmi_Mem
    151    }
    152    X86RMITag;
    153 
    154 typedef
    155    struct {
    156       X86RMITag tag;
    157       union {
    158          struct {
    159             UInt imm32;
    160          } Imm;
    161          struct {
    162             HReg reg;
    163          } Reg;
    164          struct {
    165             X86AMode* am;
    166          } Mem;
    167       }
    168       Xrmi;
    169    }
    170    X86RMI;
    171 
    172 extern X86RMI* X86RMI_Imm ( UInt );
    173 extern X86RMI* X86RMI_Reg ( HReg );
    174 extern X86RMI* X86RMI_Mem ( X86AMode* );
    175 
    176 extern void ppX86RMI ( X86RMI* );
    177 
    178 
    179 /* --------- Operand, which can be reg or immediate only. --------- */
    180 
    181 typedef
    182    enum {
    183       Xri_Imm,
    184       Xri_Reg
    185    }
    186    X86RITag;
    187 
    188 typedef
    189    struct {
    190       X86RITag tag;
    191       union {
    192          struct {
    193             UInt imm32;
    194          } Imm;
    195          struct {
    196             HReg reg;
    197          } Reg;
    198       }
    199       Xri;
    200    }
    201    X86RI;
    202 
    203 extern X86RI* X86RI_Imm ( UInt );
    204 extern X86RI* X86RI_Reg ( HReg );
    205 
    206 extern void ppX86RI ( X86RI* );
    207 
    208 
    209 /* --------- Operand, which can be reg or memory only. --------- */
    210 
    211 typedef
    212    enum {
    213       Xrm_Reg,
    214       Xrm_Mem
    215    }
    216    X86RMTag;
    217 
    218 typedef
    219    struct {
    220       X86RMTag tag;
    221       union {
    222          struct {
    223             HReg reg;
    224          } Reg;
    225          struct {
    226             X86AMode* am;
    227          } Mem;
    228       }
    229       Xrm;
    230    }
    231    X86RM;
    232 
    233 extern X86RM* X86RM_Reg ( HReg );
    234 extern X86RM* X86RM_Mem ( X86AMode* );
    235 
    236 extern void ppX86RM ( X86RM* );
    237 
    238 
    239 /* --------- Instructions. --------- */
    240 
    241 /* --------- */
    242 typedef
    243    enum {
    244       Xun_NEG,
    245       Xun_NOT
    246    }
    247    X86UnaryOp;
    248 
    249 extern HChar* showX86UnaryOp ( X86UnaryOp );
    250 
    251 
    252 /* --------- */
    253 typedef
    254    enum {
    255       Xalu_INVALID,
    256       Xalu_MOV,
    257       Xalu_CMP,
    258       Xalu_ADD, Xalu_SUB, Xalu_ADC, Xalu_SBB,
    259       Xalu_AND, Xalu_OR, Xalu_XOR,
    260       Xalu_MUL
    261    }
    262    X86AluOp;
    263 
    264 extern HChar* showX86AluOp ( X86AluOp );
    265 
    266 
    267 /* --------- */
    268 typedef
    269    enum {
    270       Xsh_INVALID,
    271       Xsh_SHL, Xsh_SHR, Xsh_SAR
    272    }
    273    X86ShiftOp;
    274 
    275 extern HChar* showX86ShiftOp ( X86ShiftOp );
    276 
    277 
    278 /* --------- */
    279 typedef
    280    enum {
    281       Xfp_INVALID,
    282       /* Binary */
    283       Xfp_ADD, Xfp_SUB, Xfp_MUL, Xfp_DIV,
    284       Xfp_SCALE, Xfp_ATAN, Xfp_YL2X, Xfp_YL2XP1, Xfp_PREM, Xfp_PREM1,
    285       /* Unary */
    286       Xfp_SQRT, Xfp_ABS, Xfp_NEG, Xfp_MOV, Xfp_SIN, Xfp_COS, Xfp_TAN,
    287       Xfp_ROUND, Xfp_2XM1
    288    }
    289    X86FpOp;
    290 
    291 extern HChar* showX86FpOp ( X86FpOp );
    292 
    293 
    294 /* --------- */
    295 typedef
    296    enum {
    297       Xsse_INVALID,
    298       /* mov */
    299       Xsse_MOV,
    300       /* Floating point binary */
    301       Xsse_ADDF, Xsse_SUBF, Xsse_MULF, Xsse_DIVF,
    302       Xsse_MAXF, Xsse_MINF,
    303       Xsse_CMPEQF, Xsse_CMPLTF, Xsse_CMPLEF, Xsse_CMPUNF,
    304       /* Floating point unary */
    305       Xsse_RCPF, Xsse_RSQRTF, Xsse_SQRTF,
    306       /* Bitwise */
    307       Xsse_AND, Xsse_OR, Xsse_XOR, Xsse_ANDN,
    308       /* Integer binary */
    309       Xsse_ADD8,   Xsse_ADD16,   Xsse_ADD32,   Xsse_ADD64,
    310       Xsse_QADD8U, Xsse_QADD16U,
    311       Xsse_QADD8S, Xsse_QADD16S,
    312       Xsse_SUB8,   Xsse_SUB16,   Xsse_SUB32,   Xsse_SUB64,
    313       Xsse_QSUB8U, Xsse_QSUB16U,
    314       Xsse_QSUB8S, Xsse_QSUB16S,
    315       Xsse_MUL16,
    316       Xsse_MULHI16U,
    317       Xsse_MULHI16S,
    318       Xsse_AVG8U, Xsse_AVG16U,
    319       Xsse_MAX16S,
    320       Xsse_MAX8U,
    321       Xsse_MIN16S,
    322       Xsse_MIN8U,
    323       Xsse_CMPEQ8,  Xsse_CMPEQ16,  Xsse_CMPEQ32,
    324       Xsse_CMPGT8S, Xsse_CMPGT16S, Xsse_CMPGT32S,
    325       Xsse_SHL16, Xsse_SHL32, Xsse_SHL64,
    326       Xsse_SHR16, Xsse_SHR32, Xsse_SHR64,
    327       Xsse_SAR16, Xsse_SAR32,
    328       Xsse_PACKSSD, Xsse_PACKSSW, Xsse_PACKUSW,
    329       Xsse_UNPCKHB, Xsse_UNPCKHW, Xsse_UNPCKHD, Xsse_UNPCKHQ,
    330       Xsse_UNPCKLB, Xsse_UNPCKLW, Xsse_UNPCKLD, Xsse_UNPCKLQ
    331    }
    332    X86SseOp;
    333 
    334 extern HChar* showX86SseOp ( X86SseOp );
    335 
    336 
    337 /* --------- */
    338 typedef
    339    enum {
    340       Xin_Alu32R,    /* 32-bit mov/arith/logical, dst=REG */
    341       Xin_Alu32M,    /* 32-bit mov/arith/logical, dst=MEM */
    342       Xin_Sh32,      /* 32-bit shift/rotate, dst=REG */
    343       Xin_Test32,    /* 32-bit test of REG or MEM against imm32 (AND, set
    344                         flags, discard result) */
    345       Xin_Unary32,   /* 32-bit not and neg */
    346       Xin_Lea32,     /* 32-bit compute EA into a reg */
    347       Xin_MulL,      /* 32 x 32 -> 64 multiply */
    348       Xin_Div,       /* 64/32 -> (32,32) div and mod */
    349       Xin_Sh3232,    /* shldl or shrdl */
    350       Xin_Push,      /* push (32-bit?) value on stack */
    351       Xin_Call,      /* call to address in register */
    352       Xin_Goto,      /* conditional/unconditional jmp to dst */
    353       Xin_CMov32,    /* conditional move */
    354       Xin_LoadEX,    /* mov{s,z}{b,w}l from mem to reg */
    355       Xin_Store,     /* store 16/8 bit value in memory */
    356       Xin_Set32,     /* convert condition code to 32-bit value */
    357       Xin_Bsfr32,    /* 32-bit bsf/bsr */
    358       Xin_MFence,    /* mem fence (not just sse2, but sse0 and 1 too) */
    359       Xin_ACAS,      /* 8/16/32-bit lock;cmpxchg */
    360       Xin_DACAS,     /* lock;cmpxchg8b (doubleword ACAS, 2 x 32-bit only) */
    361 
    362       Xin_FpUnary,   /* FP fake unary op */
    363       Xin_FpBinary,  /* FP fake binary op */
    364       Xin_FpLdSt,    /* FP fake load/store */
    365       Xin_FpLdStI,   /* FP fake load/store, converting to/from Int */
    366       Xin_Fp64to32,  /* FP round IEEE754 double to IEEE754 single */
    367       Xin_FpCMov,    /* FP fake floating point conditional move */
    368       Xin_FpLdCW,    /* fldcw */
    369       Xin_FpStSW_AX, /* fstsw %ax */
    370       Xin_FpCmp,     /* FP compare, generating a C320 value into int reg */
    371 
    372       Xin_SseConst,  /* Generate restricted SSE literal */
    373       Xin_SseLdSt,   /* SSE load/store, no alignment constraints */
    374       Xin_SseLdzLO,  /* SSE load low 32/64 bits, zero remainder of reg */
    375       Xin_Sse32Fx4,  /* SSE binary, 32Fx4 */
    376       Xin_Sse32FLo,  /* SSE binary, 32F in lowest lane only */
    377       Xin_Sse64Fx2,  /* SSE binary, 64Fx2 */
    378       Xin_Sse64FLo,  /* SSE binary, 64F in lowest lane only */
    379       Xin_SseReRg,   /* SSE binary general reg-reg, Re, Rg */
    380       Xin_SseCMov,   /* SSE conditional move */
    381       Xin_SseShuf    /* SSE2 shuffle (pshufd) */
    382    }
    383    X86InstrTag;
    384 
    385 /* Destinations are on the RIGHT (second operand) */
    386 
    387 typedef
    388    struct {
    389       X86InstrTag tag;
    390       union {
    391          struct {
    392             X86AluOp op;
    393             X86RMI*  src;
    394             HReg     dst;
    395          } Alu32R;
    396          struct {
    397             X86AluOp  op;
    398             X86RI*    src;
    399             X86AMode* dst;
    400          } Alu32M;
    401          struct {
    402             X86ShiftOp op;
    403             UInt  src;  /* shift amount, or 0 means %cl */
    404             HReg  dst;
    405          } Sh32;
    406          struct {
    407             UInt   imm32;
    408             X86RM* dst; /* not written, only read */
    409          } Test32;
    410          /* Not and Neg */
    411          struct {
    412             X86UnaryOp op;
    413             HReg       dst;
    414          } Unary32;
    415          /* 32-bit compute EA into a reg */
    416          struct {
    417             X86AMode* am;
    418             HReg      dst;
    419          } Lea32;
    420          /* EDX:EAX = EAX *s/u r/m32 */
    421          struct {
    422             Bool   syned;
    423             X86RM* src;
    424          } MulL;
    425          /* x86 div/idiv instruction.  Modifies EDX and EAX and reads src. */
    426          struct {
    427             Bool   syned;
    428             X86RM* src;
    429          } Div;
    430          /* shld/shrd.  op may only be Xsh_SHL or Xsh_SHR */
    431          struct {
    432             X86ShiftOp op;
    433             UInt       amt;   /* shift amount, or 0 means %cl */
    434             HReg       src;
    435             HReg       dst;
    436          } Sh3232;
    437          struct {
    438             X86RMI* src;
    439          } Push;
    440          /* Pseudo-insn.  Call target (an absolute address), on given
    441             condition (which could be Xcc_ALWAYS). */
    442          struct {
    443             X86CondCode cond;
    444             Addr32      target;
    445             Int         regparms; /* 0 .. 3 */
    446          } Call;
    447          /* Pseudo-insn.  Goto dst, on given condition (which could be
    448             Xcc_ALWAYS). */
    449          struct {
    450             IRJumpKind  jk;
    451             X86CondCode cond;
    452             X86RI*      dst;
    453          } Goto;
    454          /* Mov src to dst on the given condition, which may not
    455             be the bogus Xcc_ALWAYS. */
    456          struct {
    457             X86CondCode cond;
    458             X86RM*      src;
    459             HReg        dst;
    460          } CMov32;
    461          /* Sign/Zero extending loads.  Dst size is always 32 bits. */
    462          struct {
    463             UChar     szSmall;
    464             Bool      syned;
    465             X86AMode* src;
    466             HReg      dst;
    467          } LoadEX;
    468          /* 16/8 bit stores, which are troublesome (particularly
    469             8-bit) */
    470          struct {
    471             UChar     sz; /* only 1 or 2 */
    472             HReg      src;
    473             X86AMode* dst;
    474          } Store;
    475          /* Convert a x86 condition code to a 32-bit value (0 or 1). */
    476          struct {
    477             X86CondCode cond;
    478             HReg        dst;
    479          } Set32;
    480          /* 32-bit bsf or bsr. */
    481          struct {
    482             Bool isFwds;
    483             HReg src;
    484             HReg dst;
    485          } Bsfr32;
    486          /* Mem fence (not just sse2, but sse0 and 1 too).  In short,
    487             an insn which flushes all preceding loads and stores as
    488             much as possible before continuing.  On SSE2 we emit a
    489             real "mfence", on SSE1 "sfence ; lock addl $0,0(%esp)" and
    490             on SSE0 "lock addl $0,0(%esp)".  This insn therefore
    491             carries the host's hwcaps so the assembler knows what to
    492             emit. */
    493          struct {
    494             UInt hwcaps;
    495          } MFence;
    496          /* "lock;cmpxchg": mem address in .addr,
    497              expected value in %eax, new value in %ebx */
    498          struct {
    499             X86AMode* addr;
    500             UChar     sz; /* 1, 2 or 4 */
    501          } ACAS;
    502          /* "lock;cmpxchg8b": mem address in .addr, expected value in
    503             %edx:%eax, new value in %ecx:%ebx */
    504          struct {
    505             X86AMode* addr;
    506          } DACAS;
    507 
    508          /* X86 Floating point (fake 3-operand, "flat reg file" insns) */
    509          struct {
    510             X86FpOp op;
    511             HReg    src;
    512             HReg    dst;
    513          } FpUnary;
    514          struct {
    515             X86FpOp op;
    516             HReg    srcL;
    517             HReg    srcR;
    518             HReg    dst;
    519          } FpBinary;
    520          struct {
    521             Bool      isLoad;
    522             UChar     sz; /* only 4 (IEEE single) or 8 (IEEE double) */
    523             HReg      reg;
    524             X86AMode* addr;
    525          } FpLdSt;
    526          /* Move 64-bit float to/from memory, converting to/from
    527             signed int on the way.  Note the conversions will observe
    528             the host FPU rounding mode currently in force. */
    529          struct {
    530             Bool      isLoad;
    531             UChar     sz; /* only 2, 4 or 8 */
    532             HReg      reg;
    533             X86AMode* addr;
    534          } FpLdStI;
    535          /* By observing the current FPU rounding mode, round (etc)
    536             src into dst given that dst should be interpreted as an
    537             IEEE754 32-bit (float) type. */
    538          struct {
    539             HReg src;
    540             HReg dst;
    541          } Fp64to32;
    542          /* Mov src to dst on the given condition, which may not
    543             be the bogus Xcc_ALWAYS. */
    544          struct {
    545             X86CondCode cond;
    546             HReg        src;
    547             HReg        dst;
    548          } FpCMov;
    549          /* Load the FPU's 16-bit control word (fldcw) */
    550          struct {
    551             X86AMode* addr;
    552          }
    553          FpLdCW;
    554          /* fstsw %ax */
    555          struct {
    556             /* no fields */
    557          }
    558          FpStSW_AX;
    559          /* Do a compare, generating the C320 bits into the dst. */
    560          struct {
    561             HReg    srcL;
    562             HReg    srcR;
    563             HReg    dst;
    564          } FpCmp;
    565 
    566          /* Simplistic SSE[123] */
    567          struct {
    568             UShort  con;
    569             HReg    dst;
    570          } SseConst;
    571          struct {
    572             Bool      isLoad;
    573             HReg      reg;
    574             X86AMode* addr;
    575          } SseLdSt;
    576          struct {
    577             UChar     sz; /* 4 or 8 only */
    578             HReg      reg;
    579             X86AMode* addr;
    580          } SseLdzLO;
    581          struct {
    582             X86SseOp op;
    583             HReg     src;
    584             HReg     dst;
    585          } Sse32Fx4;
    586          struct {
    587             X86SseOp op;
    588             HReg     src;
    589             HReg     dst;
    590          } Sse32FLo;
    591          struct {
    592             X86SseOp op;
    593             HReg     src;
    594             HReg     dst;
    595          } Sse64Fx2;
    596          struct {
    597             X86SseOp op;
    598             HReg     src;
    599             HReg     dst;
    600          } Sse64FLo;
    601          struct {
    602             X86SseOp op;
    603             HReg     src;
    604             HReg     dst;
    605          } SseReRg;
    606          /* Mov src to dst on the given condition, which may not
    607             be the bogus Xcc_ALWAYS. */
    608          struct {
    609             X86CondCode cond;
    610             HReg        src;
    611             HReg        dst;
    612          } SseCMov;
    613          struct {
    614             Int    order; /* 0 <= order <= 0xFF */
    615             HReg   src;
    616             HReg   dst;
    617          } SseShuf;
    618 
    619       } Xin;
    620    }
    621    X86Instr;
    622 
    623 extern X86Instr* X86Instr_Alu32R    ( X86AluOp, X86RMI*, HReg );
    624 extern X86Instr* X86Instr_Alu32M    ( X86AluOp, X86RI*,  X86AMode* );
    625 extern X86Instr* X86Instr_Unary32   ( X86UnaryOp op, HReg dst );
    626 extern X86Instr* X86Instr_Lea32     ( X86AMode* am, HReg dst );
    627 
    628 extern X86Instr* X86Instr_Sh32      ( X86ShiftOp, UInt, HReg );
    629 extern X86Instr* X86Instr_Test32    ( UInt imm32, X86RM* dst );
    630 extern X86Instr* X86Instr_MulL      ( Bool syned, X86RM* );
    631 extern X86Instr* X86Instr_Div       ( Bool syned, X86RM* );
    632 extern X86Instr* X86Instr_Sh3232    ( X86ShiftOp, UInt amt, HReg src, HReg dst );
    633 extern X86Instr* X86Instr_Push      ( X86RMI* );
    634 extern X86Instr* X86Instr_Call      ( X86CondCode, Addr32, Int );
    635 extern X86Instr* X86Instr_Goto      ( IRJumpKind, X86CondCode cond, X86RI* dst );
    636 extern X86Instr* X86Instr_CMov32    ( X86CondCode, X86RM* src, HReg dst );
    637 extern X86Instr* X86Instr_LoadEX    ( UChar szSmall, Bool syned,
    638                                       X86AMode* src, HReg dst );
    639 extern X86Instr* X86Instr_Store     ( UChar sz, HReg src, X86AMode* dst );
    640 extern X86Instr* X86Instr_Set32     ( X86CondCode cond, HReg dst );
    641 extern X86Instr* X86Instr_Bsfr32    ( Bool isFwds, HReg src, HReg dst );
    642 extern X86Instr* X86Instr_MFence    ( UInt hwcaps );
    643 extern X86Instr* X86Instr_ACAS      ( X86AMode* addr, UChar sz );
    644 extern X86Instr* X86Instr_DACAS     ( X86AMode* addr );
    645 
    646 extern X86Instr* X86Instr_FpUnary   ( X86FpOp op, HReg src, HReg dst );
    647 extern X86Instr* X86Instr_FpBinary  ( X86FpOp op, HReg srcL, HReg srcR, HReg dst );
    648 extern X86Instr* X86Instr_FpLdSt    ( Bool isLoad, UChar sz, HReg reg, X86AMode* );
    649 extern X86Instr* X86Instr_FpLdStI   ( Bool isLoad, UChar sz, HReg reg, X86AMode* );
    650 extern X86Instr* X86Instr_Fp64to32  ( HReg src, HReg dst );
    651 extern X86Instr* X86Instr_FpCMov    ( X86CondCode, HReg src, HReg dst );
    652 extern X86Instr* X86Instr_FpLdCW    ( X86AMode* );
    653 extern X86Instr* X86Instr_FpStSW_AX ( void );
    654 extern X86Instr* X86Instr_FpCmp     ( HReg srcL, HReg srcR, HReg dst );
    655 
    656 extern X86Instr* X86Instr_SseConst  ( UShort con, HReg dst );
    657 extern X86Instr* X86Instr_SseLdSt   ( Bool isLoad, HReg, X86AMode* );
    658 extern X86Instr* X86Instr_SseLdzLO  ( Int sz, HReg, X86AMode* );
    659 extern X86Instr* X86Instr_Sse32Fx4  ( X86SseOp, HReg, HReg );
    660 extern X86Instr* X86Instr_Sse32FLo  ( X86SseOp, HReg, HReg );
    661 extern X86Instr* X86Instr_Sse64Fx2  ( X86SseOp, HReg, HReg );
    662 extern X86Instr* X86Instr_Sse64FLo  ( X86SseOp, HReg, HReg );
    663 extern X86Instr* X86Instr_SseReRg   ( X86SseOp, HReg, HReg );
    664 extern X86Instr* X86Instr_SseCMov   ( X86CondCode, HReg src, HReg dst );
    665 extern X86Instr* X86Instr_SseShuf   ( Int order, HReg src, HReg dst );
    666 
    667 
    668 extern void ppX86Instr ( X86Instr*, Bool );
    669 
    670 /* Some functions that insulate the register allocator from details
    671    of the underlying instruction set. */
    672 extern void         getRegUsage_X86Instr ( HRegUsage*, X86Instr*, Bool );
    673 extern void         mapRegs_X86Instr     ( HRegRemap*, X86Instr*, Bool );
    674 extern Bool         isMove_X86Instr      ( X86Instr*, HReg*, HReg* );
    675 extern Int          emit_X86Instr        ( UChar* buf, Int nbuf, X86Instr*,
    676                                            Bool,
    677                                            void* dispatch_unassisted,
    678                                            void* dispatch_assisted );
    679 
    680 extern void genSpill_X86  ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
    681                             HReg rreg, Int offset, Bool );
    682 extern void genReload_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
    683                             HReg rreg, Int offset, Bool );
    684 
    685 extern X86Instr*    directReload_X86     ( X86Instr* i,
    686                                            HReg vreg, Short spill_off );
    687 extern void         getAllocableRegs_X86 ( Int*, HReg** );
    688 extern HInstrArray* iselSB_X86           ( IRSB*, VexArch,
    689                                                   VexArchInfo*,
    690                                                   VexAbiInfo* );
    691 
    692 #endif /* ndef __VEX_HOST_X86_DEFS_H */
    693 
    694 /*---------------------------------------------------------------*/
    695 /*--- end                                     host_x86_defs.h ---*/
    696 /*---------------------------------------------------------------*/
    697