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    Searched defs:IndexReg (Results 1 - 8 of 8) sorted by null

  /external/llvm/lib/Target/X86/InstPrinter/
X86ATTInstPrinter.cpp 139 const MCOperand &IndexReg = MI->getOperand(Op+2);
151 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
158 if (IndexReg.getReg() || BaseReg.getReg()) {
163 if (IndexReg.getReg()) {
X86IntelInstPrinter.cpp 131 const MCOperand &IndexReg = MI->getOperand(Op+2);
149 if (IndexReg.getReg()) {
164 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
  /external/llvm/lib/Target/X86/
X86InstrBuilder.h 49 unsigned IndexReg;
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
72 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
133 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
X86AsmPrinter.cpp 307 const MachineOperand &IndexReg = MI->getOperand(Op+2);
317 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
333 assert(IndexReg.getReg() != X86::ESP &&
340 if (IndexReg.getReg()) {
X86FastISel.cpp 409 unsigned IndexReg = AM.IndexReg;
446 if (IndexReg == 0 &&
451 IndexReg = getRegForGEPIndex(Op).first;
452 if (IndexReg == 0)
465 AM.IndexReg = IndexReg;
504 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
523 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
585 if (AM.IndexReg == 0)
    [all...]
X86ISelDAGToDAG.cpp 63 SDValue IndexReg;
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
85 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
112 << "IndexReg ";
113 if (IndexReg.getNode() != 0)
114 IndexReg.getNode()->dump();
236 Index = AM.IndexReg;
708 AM.Base_Reg = AM.IndexReg;
720 AM.IndexReg.getNode() == 0 &&
779 AM.IndexReg = And
    [all...]
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 166 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
170 (IndexReg.getReg() != 0 &&
171 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
181 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
185 (IndexReg.getReg() != 0 &&
186 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
196 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
200 (IndexReg.getReg() != 0 &&
201 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
304 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg)
    [all...]
  /external/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp 177 unsigned IndexReg;
229 return Mem.IndexReg;
426 Res->Mem.IndexReg = 0;
434 unsigned BaseReg, unsigned IndexReg,
439 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
448 Res->Mem.IndexReg = IndexReg;
464 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
474 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
604 unsigned BaseReg = 0, IndexReg = 0, Scale = 1
    [all...]

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