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      1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the X86 specific subclass of TargetMachine.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "X86TargetMachine.h"
     15 #include "X86.h"
     16 #include "llvm/PassManager.h"
     17 #include "llvm/CodeGen/MachineFunction.h"
     18 #include "llvm/CodeGen/Passes.h"
     19 #include "llvm/Support/CommandLine.h"
     20 #include "llvm/Support/FormattedStream.h"
     21 #include "llvm/Target/TargetOptions.h"
     22 #include "llvm/Support/TargetRegistry.h"
     23 using namespace llvm;
     24 
     25 extern "C" void LLVMInitializeX86Target() {
     26   // Register the target.
     27   RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
     28   RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
     29 }
     30 
     31 void X86_32TargetMachine::anchor() { }
     32 
     33 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
     34                                          StringRef CPU, StringRef FS,
     35                                          const TargetOptions &Options,
     36                                          Reloc::Model RM, CodeModel::Model CM,
     37                                          CodeGenOpt::Level OL)
     38   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
     39     DataLayout(getSubtargetImpl()->isTargetDarwin() ?
     40                "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
     41                "n8:16:32-S128" :
     42                (getSubtargetImpl()->isTargetCygMing() ||
     43                 getSubtargetImpl()->isTargetWindows()) ?
     44                "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
     45                "n8:16:32-S32" :
     46                "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
     47                "n8:16:32-S128"),
     48     InstrInfo(*this),
     49     TSInfo(*this),
     50     TLInfo(*this),
     51     JITInfo(*this) {
     52 }
     53 
     54 void X86_64TargetMachine::anchor() { }
     55 
     56 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
     57                                          StringRef CPU, StringRef FS,
     58                                          const TargetOptions &Options,
     59                                          Reloc::Model RM, CodeModel::Model CM,
     60                                          CodeGenOpt::Level OL)
     61   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
     62     DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
     63                "n8:16:32:64-S128"),
     64     InstrInfo(*this),
     65     TSInfo(*this),
     66     TLInfo(*this),
     67     JITInfo(*this) {
     68 }
     69 
     70 /// X86TargetMachine ctor - Create an X86 target.
     71 ///
     72 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
     73                                    StringRef CPU, StringRef FS,
     74                                    const TargetOptions &Options,
     75                                    Reloc::Model RM, CodeModel::Model CM,
     76                                    CodeGenOpt::Level OL,
     77                                    bool is64Bit)
     78   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
     79     Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
     80     FrameLowering(*this, Subtarget),
     81     ELFWriterInfo(is64Bit, true),
     82     InstrItins(Subtarget.getInstrItineraryData()){
     83   // Determine the PICStyle based on the target selected.
     84   if (getRelocationModel() == Reloc::Static) {
     85     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
     86     Subtarget.setPICStyle(PICStyles::None);
     87   } else if (Subtarget.is64Bit()) {
     88     // PIC in 64 bit mode is always rip-rel.
     89     Subtarget.setPICStyle(PICStyles::RIPRel);
     90   } else if (Subtarget.isTargetCygMing()) {
     91     Subtarget.setPICStyle(PICStyles::None);
     92   } else if (Subtarget.isTargetDarwin()) {
     93     if (getRelocationModel() == Reloc::PIC_)
     94       Subtarget.setPICStyle(PICStyles::StubPIC);
     95     else {
     96       assert(getRelocationModel() == Reloc::DynamicNoPIC);
     97       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
     98     }
     99   } else if (Subtarget.isTargetELF()) {
    100     Subtarget.setPICStyle(PICStyles::GOT);
    101   }
    102 
    103   // default to hard float ABI
    104   if (Options.FloatABIType == FloatABI::Default)
    105     this->Options.FloatABIType = FloatABI::Hard;
    106 }
    107 
    108 //===----------------------------------------------------------------------===//
    109 // Command line options for x86
    110 //===----------------------------------------------------------------------===//
    111 static cl::opt<bool>
    112 UseVZeroUpper("x86-use-vzeroupper",
    113   cl::desc("Minimize AVX to SSE transition penalty"),
    114   cl::init(true));
    115 
    116 //===----------------------------------------------------------------------===//
    117 // Pass Pipeline Configuration
    118 //===----------------------------------------------------------------------===//
    119 
    120 namespace {
    121 /// X86 Code Generator Pass Configuration Options.
    122 class X86PassConfig : public TargetPassConfig {
    123 public:
    124   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
    125     : TargetPassConfig(TM, PM) {}
    126 
    127   X86TargetMachine &getX86TargetMachine() const {
    128     return getTM<X86TargetMachine>();
    129   }
    130 
    131   const X86Subtarget &getX86Subtarget() const {
    132     return *getX86TargetMachine().getSubtargetImpl();
    133   }
    134 
    135   virtual bool addInstSelector();
    136   virtual bool addPreRegAlloc();
    137   virtual bool addPostRegAlloc();
    138   virtual bool addPreEmitPass();
    139 };
    140 } // namespace
    141 
    142 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
    143   return new X86PassConfig(this, PM);
    144 }
    145 
    146 bool X86PassConfig::addInstSelector() {
    147   // Install an instruction selector.
    148   PM.add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
    149 
    150   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
    151   if (!getX86Subtarget().is64Bit())
    152     PM.add(createGlobalBaseRegPass());
    153 
    154   return false;
    155 }
    156 
    157 bool X86PassConfig::addPreRegAlloc() {
    158   PM.add(createX86MaxStackAlignmentHeuristicPass());
    159   return false;  // -print-machineinstr shouldn't print after this.
    160 }
    161 
    162 bool X86PassConfig::addPostRegAlloc() {
    163   PM.add(createX86FloatingPointStackifierPass());
    164   return true;  // -print-machineinstr should print after this.
    165 }
    166 
    167 bool X86PassConfig::addPreEmitPass() {
    168   bool ShouldPrint = false;
    169   if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
    170     PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
    171     ShouldPrint = true;
    172   }
    173 
    174   if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
    175     PM.add(createX86IssueVZeroUpperPass());
    176     ShouldPrint = true;
    177   }
    178 
    179   return ShouldPrint;
    180 }
    181 
    182 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
    183                                       JITCodeEmitter &JCE) {
    184   PM.add(createX86JITCodeEmitterPass(*this, JCE));
    185 
    186   return false;
    187 }
    188