| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 504 unsigned NewOpc = convertToNonSPOpcode(Opcode);
505 if (NewOpc != Opcode && FrameReg != ARM::SP)
506 MI.setDesc(TII.get(NewOpc));
|
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 778 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
779 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
877 unsigned NewOpc = 0;
895 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);
914 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);
932 BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
941 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
943 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
948 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | [all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 609 unsigned NewOpc = 0;
623 NewOpc = SPU::AIr32;
628 NewOpc = SPU::Ar32;
861 NewOpc = SPU::Ar32;
867 NewOpc = SPU::AIr32;
883 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
885 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
[all...] |
| SPUISelLowering.cpp | 741 unsigned NewOpc = ISD::ANY_EXTEND;
744 NewOpc = ISD::FP_EXTEND;
746 result = DAG.getNode(NewOpc, dl, OutVT, result);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 353 unsigned NewOpc = N->getOpcode();
363 NewOpc = ISD::FP_TO_SINT;
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
