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      1 #define OFFSET_x86_EAX 0
      2 #define OFFSET_x86_EBX 12
      3 #define OFFSET_x86_ECX 4
      4 #define OFFSET_x86_EDX 8
      5 #define OFFSET_x86_ESI 24
      6 #define OFFSET_x86_EDI 28
      7 #define OFFSET_x86_EBP 20
      8 #define OFFSET_x86_ESP 16
      9 #define OFFSET_x86_EIP 60
     10 #define OFFSET_x86_CS 280
     11 #define OFFSET_x86_DS 282
     12 #define OFFSET_x86_ES 284
     13 #define OFFSET_x86_FS 286
     14 #define OFFSET_x86_GS 288
     15 #define OFFSET_x86_SS 290
     16 #define OFFSET_amd64_RAX 0
     17 #define OFFSET_amd64_RBX 24
     18 #define OFFSET_amd64_RCX 8
     19 #define OFFSET_amd64_RDX 16
     20 #define OFFSET_amd64_RSI 48
     21 #define OFFSET_amd64_RDI 56
     22 #define OFFSET_amd64_RSP 32
     23 #define OFFSET_amd64_RBP 40
     24 #define OFFSET_amd64_R8 64
     25 #define OFFSET_amd64_R9 72
     26 #define OFFSET_amd64_R10 80
     27 #define OFFSET_amd64_R11 88
     28 #define OFFSET_amd64_R12 96
     29 #define OFFSET_amd64_R13 104
     30 #define OFFSET_amd64_R14 112
     31 #define OFFSET_amd64_R15 120
     32 #define OFFSET_amd64_RIP 168
     33 #define OFFSET_ppc32_GPR0 0
     34 #define OFFSET_ppc32_GPR1 4
     35 #define OFFSET_ppc32_GPR2 8
     36 #define OFFSET_ppc32_GPR3 12
     37 #define OFFSET_ppc32_GPR4 16
     38 #define OFFSET_ppc32_GPR5 20
     39 #define OFFSET_ppc32_GPR6 24
     40 #define OFFSET_ppc32_GPR7 28
     41 #define OFFSET_ppc32_GPR8 32
     42 #define OFFSET_ppc32_GPR9 36
     43 #define OFFSET_ppc32_GPR10 40
     44 #define OFFSET_ppc32_CIA 1152
     45 #define OFFSET_ppc32_CR0_0 1169
     46 #define OFFSET_ppc64_GPR0 0
     47 #define OFFSET_ppc64_GPR1 8
     48 #define OFFSET_ppc64_GPR2 16
     49 #define OFFSET_ppc64_GPR3 24
     50 #define OFFSET_ppc64_GPR4 32
     51 #define OFFSET_ppc64_GPR5 40
     52 #define OFFSET_ppc64_GPR6 48
     53 #define OFFSET_ppc64_GPR7 56
     54 #define OFFSET_ppc64_GPR8 64
     55 #define OFFSET_ppc64_GPR9 72
     56 #define OFFSET_ppc64_GPR10 80
     57 #define OFFSET_ppc64_CIA 1280
     58 #define OFFSET_ppc64_CR0_0 1309
     59 #define OFFSET_arm_R0 0
     60 #define OFFSET_arm_R1 4
     61 #define OFFSET_arm_R2 8
     62 #define OFFSET_arm_R3 12
     63 #define OFFSET_arm_R4 16
     64 #define OFFSET_arm_R5 20
     65 #define OFFSET_arm_R7 28
     66 #define OFFSET_arm_R13 52
     67 #define OFFSET_arm_R14 56
     68 #define OFFSET_arm_R15T 60
     69 #define OFFSET_s390x_r2 208
     70 #define OFFSET_s390x_r3 216
     71 #define OFFSET_s390x_r4 224
     72 #define OFFSET_s390x_r5 232
     73 #define OFFSET_s390x_r6 240
     74 #define OFFSET_s390x_r7 248
     75 #define OFFSET_s390x_r15 312
     76 #define OFFSET_s390x_IA 336
     77 #define OFFSET_s390x_SYSNO 344
     78 #define OFFSET_s390x_IP_AT_SYSCALL 408
     79 #define OFFSET_s390x_fpc 328
     80