/external/llvm/lib/Target/Mips/ |
MipsMachineFunction.cpp | 43 const TargetRegisterClass *RC; 44 RC = ST.isABI_N64() ? 47 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
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/external/llvm/lib/CodeGen/ |
AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); 45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint, 65 ArrayRef<unsigned> O = RCI.getOrder(RC); 72 !RC->contains(Hint) || RCI.isReserved(Hint)))
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LiveStackAnalysis.cpp | 55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { 61 S2RCMap.insert(std::make_pair(Slot, RC)); 65 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 77 const TargetRegisterClass *RC = getIntervalRegClass(Slot); 78 if (RC) 79 OS << " [" << RC->getName() << "]\n";
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AggressiveAntiDepBreaker.h | 44 /// RC - The register class 45 const TargetRegisterClass *RC;
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VirtRegMap.cpp | 71 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) { 72 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(), 73 RC->getAlignment()); 93 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); 94 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
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LocalStackSlotAllocation.cpp | 317 const TargetRegisterClass *RC = TRI->getPointerRegClass(); 318 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
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ProcessImplicitDefs.cpp | 280 const TargetRegisterClass* RC = MRI->getRegClass(Reg); 281 unsigned NewVReg = MRI->createVirtualRegister(RC);
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CriticalAntiDepBreaker.cpp | 402 const TargetRegisterClass *RC) 404 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC); 615 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0; 616 assert((AntiDepReg == 0 || RC != NULL) && 618 if (RC == reinterpret_cast<TargetRegisterClass *>(-1)) 632 RC)) {
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PHIElimination.cpp | 231 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); 232 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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PeepholeOptimizer.cpp | 232 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); 244 unsigned NewVR = MRI->createVirtualRegister(RC);
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TargetInstrInfoImpl.cpp | 278 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); 281 return RC->contains(LiveOp.getReg()) ? RC : 0; 283 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) 284 return RC; 342 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); 343 if (!RC) 351 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); 353 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
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/external/llvm/lib/Target/ |
TargetRegisterInfo.cpp | 60 const TargetRegisterClass* RC = *I; 61 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 62 (!BestRC || BestRC->hasSubClass(RC))) 63 BestRC = RC; 73 const TargetRegisterClass *RC, BitVector &R){ 74 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); 80 const TargetRegisterClass *RC) const { 82 if (RC) { 83 getAllocatableSetForRC(MF, RC, Allocatable) [all...] |
/external/dropbear/libtomcrypt/src/ciphers/ |
noekeon.c | 33 static const ulong32 RC[] = { 129 a ^= RC[i]; \ 141 a ^= RC[16]; 185 a ^= RC[i]; \ 197 a ^= RC[0];
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/external/llvm/lib/Target/CellSPU/ |
SPUFrameLowering.cpp | 252 const TargetRegisterClass *RC = &SPU::R32CRegClass; 253 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 254 RC->getAlignment(),
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/external/llvm/utils/TableGen/ |
FastISelEmitter.cpp | 35 const CodeGenRegisterClass *RC; 249 const CodeGenRegisterClass *RC = 0; 253 RC = &Target.getRegisterClass(OpLeafRec); 255 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 260 if (!RC) 266 if (DstRC != RC && !DstRC->hasSubClass(RC)) 269 DstRC = RC; 642 OS << InstNS << Memo.RC->getName() << "RegisterClass"; 734 OS << InstNS << Memo.RC->getName() << "RegisterClass" [all...] |
CodeGenTarget.cpp | 211 const CodeGenRegisterClass &RC = *RCs[i]; 212 if (RC.contains(Reg)) { 213 const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes(); 369 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, 371 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
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/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 116 const TargetRegisterClass *RC = 0; 118 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI); 120 UseRC = RC; 121 else if (RC) { 123 TRI->getCommonSubClass(UseRC, RC); 199 const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI); 218 if (RegRC == RC) { 230 assert(RC && "Isn't a register operand!"); 231 VRBase = MRI->createVirtualRegister(RC); 255 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()) [all...] |
ResourcePriorityQueue.cpp | 370 const TargetRegisterClass *RC = *I; 371 RegBalance += rawRegPressureDelta(SU, RC->getID()); 377 const TargetRegisterClass *RC = *I; 378 if ((RegPressure[RC->getID()] + 379 rawRegPressureDelta(SU, RC->getID()) > 0) && 380 (RegPressure[RC->getID()] + 381 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) 382 RegBalance += rawRegPressureDelta(SU, RC->getID()); 491 const TargetRegisterClass *RC = TLI->getRegClassFor(VT) [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonFrameLowering.cpp | 262 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 263 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RC, 321 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 322 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
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/external/llvm/lib/Target/X86/ |
X86VZeroUpper.cpp | 148 const TargetRegisterClass *RC = X86::VR256RegisterClass; 149 for (TargetRegisterClass::iterator i = RC->begin(), e = RC->end();
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/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 173 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 178 switch (RC->getID()) { 242 const TargetRegisterClass *RC, int SPAdj) { 244 unsigned Reg = RS->FindUnusedReg(RC); 248 Reg = RS->scavengeRegister(RC, II, SPAdj); 292 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 297 Reg = findScratchRegister(II, RS, RC, SPAdj);
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/external/llvm/lib/Target/XCore/ |
XCoreFrameLowering.cpp | 295 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 297 it->getFrameIdx(), RC, TRI); 321 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 323 RC, TRI); 344 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass; 353 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true); 355 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), 363 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 364 RC->getAlignment() [all...] |
/external/clang/test/SemaCXX/ |
nested-name-spec.cpp | 71 struct RC; 77 struct A2::RC { 101 void f6(int A2::RC::x); // expected-error{{parameter declarator cannot be qualified}} 103 int A2::RC::x; // expected-error{{non-static data member defined out-of-line}}
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/external/expat/bcb5/ |
elements.mak | 146 .PATH.RC = $(PATHRC) 180 .rc.res:
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expat.mak | 147 .PATH.RC = $(PATHRC) 181 .rc.res:
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