1 /* 2 * Device.h 3 * 4 * Copyright(c) 1998 - 2009 Texas Instruments. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name Texas Instruments nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /**************************************************************************** 36 * 37 * MODULE: Device.h 38 * PURPOSE: Contains Wlan hardware registers defines/structures 39 * 40 ****************************************************************************/ 41 42 #ifndef DEVICE_H 43 #define DEVICE_H 44 45 #include "Device1273.h" 46 47 48 #define ACX_PHI_CCA_THRSH_ENABLE_ENERGY_D 0x140A 49 #define ACX_PHI_CCA_THRSH_DISABLE_ENERGY_D 0xFFEF 50 51 /* 52 * Wlan hardware Registers. 53 */ 54 55 /*====================================================================== 56 Interrupt Registers 57 =======================================================================*/ 58 59 #define ACX_REG_INTERRUPT_TRIG ( INT_TRIG ) 60 61 #define ACX_REG_INTERRUPT_TRIG_H ( INT_TRIG_H ) 62 63 /*============================================= 64 Host Interrupt Mask Register - 32bit (RW) 65 ------------------------------------------ 66 Setting a bit in this register masks the 67 corresponding interrupt to the host. 68 0 - RX0 - Rx first dubble buffer Data Interrupt 69 1 - TXD - Tx Data Interrupt 70 2 - TXXFR - Tx Transfer Interrupt 71 3 - RX1 - Rx second dubble buffer Data Interrupt 72 4 - RXXFR - Rx Transfer Interrupt 73 5 - EVENT_A - Event Mailbox interrupt 74 6 - EVENT_B - Event Mailbox interrupt 75 7 - WNONHST - Wake On Host Interrupt 76 8 - TRACE_A - Debug Trace interrupt 77 9 - TRACE_B - Debug Trace interrupt 78 10 - CDCMP - Command Complete Interrupt 79 11 - 80 12 - 81 13 - 82 14 - ICOMP - Initialization Complete Interrupt 83 16 - SG SE - Soft Gemini - Sense enable interrupt 84 17 - SG SD - Soft Gemini - Sense disable interrupt 85 18 - - 86 19 - - 87 20 - - 88 21- - 89 Default: 0x0001 90 *==============================================*/ 91 #define ACX_REG_INTERRUPT_MASK ( HINT_MASK ) 92 93 /*============================================= 94 Host Interrupt Mask Set 16bit, (Write only) 95 ------------------------------------------ 96 Setting a bit in this register sets 97 the corresponding bin in ACX_HINT_MASK register 98 without effecting the mask 99 state of other bits (0 = no effect). 100 ==============================================*/ 101 #define ACX_HINT_MASK_SET_REG HINT_MASK_SET 102 103 /*============================================= 104 Host Interrupt Mask Clear 16bit,(Write only) 105 ------------------------------------------ 106 Setting a bit in this register clears 107 the corresponding bin in ACX_HINT_MASK register 108 without effecting the mask 109 state of other bits (0 = no effect). 110 =============================================*/ 111 #define ACX_HINT_MASK_CLR_REG HINT_MASK_CLR 112 113 /*============================================= 114 Host Interrupt Status Nondestructive Read 115 16bit,(Read only) 116 ------------------------------------------ 117 The host can read this register to determine 118 which interrupts are active. 119 Reading this register doesn't 120 effect its content. 121 =============================================*/ 122 #define ACX_REG_INTERRUPT_NO_CLEAR ( HINT_STS_ND ) 123 124 /*============================================= 125 Host Interrupt Status Clear on Read Register 126 16bit,(Read only) 127 ------------------------------------------ 128 The host can read this register to determine 129 which interrupts are active. 130 Reading this register clears it, 131 thus making all interrupts inactive. 132 ==============================================*/ 133 #define ACX_REG_INTERRUPT_CLEAR ( HINT_STS_CLR ) 134 135 /*============================================= 136 Host Interrupt Acknowledge Register 137 16bit,(Write only) 138 ------------------------------------------ 139 The host can set individual bits in this 140 register to clear (acknowledge) the corresp. 141 interrupt status bits in the HINT_STS_CLR and 142 HINT_STS_ND registers, thus making the 143 assotiated interrupt inactive. (0-no effect) 144 ==============================================*/ 145 #define ACX_REG_INTERRUPT_ACK ( HINT_ACK ) 146 147 148 /*=============================================== 149 Host Software Reset - 32bit RW 150 ------------------------------------------ 151 [31:1] Reserved 152 0 SOFT_RESET Soft Reset - When this bit is set, 153 it holds the Wlan hardware in a soft reset state. 154 This reset disables all MAC and baseband processor 155 clocks except the CardBus/PCI interface clock. 156 It also initializes all MAC state machines except 157 the host interface. It does not reload the 158 contents of the EEPROM. When this bit is cleared 159 (not self-clearing), the Wlan hardware 160 exits the software reset state. 161 ===============================================*/ 162 #define ACX_REG_SLV_SOFT_RESET ( SLV_SOFT_RESET ) 163 #define SLV_SOFT_RESET_BIT 0x00000001 164 165 /*=============================================== 166 EEPROM Burst Read Start - 32bit RW 167 ------------------------------------------ 168 [31:1] Reserved 169 0 ACX_EE_START - EEPROM Burst Read Start 0 170 Setting this bit starts a burst read from 171 the external EEPROM. 172 If this bit is set (after reset) before an EEPROM read/write, 173 the burst read starts at EEPROM address 0. 174 Otherwise, it starts at the address 175 following the address of the previous access. 176 TheWlan hardware hardware clears this bit automatically. 177 178 Default: 0x00000000 179 *================================================*/ 180 #define ACX_REG_EE_START ( EE_START ) 181 #define START_EEPROM_MGR 0x00000001 182 183 /*======================================================================= 184 Embedded ARM CPU Control 185 ========================================================================*/ 186 /*=============================================== 187 Halt eCPU - 32bit RW 188 ------------------------------------------ 189 0 HALT_ECPU Halt Embedded CPU - This bit is the 190 compliment of bit 1 (MDATA2) in the SOR_CFG register. 191 During a hardware reset, this bit holds 192 the inverse of MDATA2. 193 When downloading firmware from the host, 194 set this bit (pull down MDATA2). 195 The host clears this bit after downloading the firmware into 196 zero-wait-state SSRAM. 197 When loading firmware from Flash, clear this bit (pull up MDATA2) 198 so that the eCPU can run the bootloader code in Flash 199 HALT_ECPU eCPU State 200 -------------------- 201 1 halt eCPU 202 0 enable eCPU 203 ===============================================*/ 204 #define ACX_REG_ECPU_CONTROL ( ECPU_CTRL ) 205 206 207 /*======================================================================= 208 Command/Information Mailbox Pointers 209 ========================================================================*/ 210 211 /*=============================================== 212 Command Mailbox Pointer - 32bit RW 213 ------------------------------------------ 214 This register holds the start address of 215 the command mailbox located in the Wlan hardware memory. 216 The host must read this pointer after a reset to 217 find the location of the command mailbox. 218 The Wlan hardware initializes the command mailbox 219 pointer with the default address of the command mailbox. 220 The command mailbox pointer is not valid until after 221 the host receives the Init Complete interrupt from 222 the Wlan hardware. 223 ===============================================*/ 224 #define REG_COMMAND_MAILBOX_PTR ( SCR_PAD0 ) 225 226 /*=============================================== 227 Information Mailbox Pointer - 32bit RW 228 ------------------------------------------ 229 This register holds the start address of 230 the information mailbox located in the Wlan hardware memory. 231 The host must read this pointer after a reset to find 232 the location of the information mailbox. 233 The Wlan hardware initializes the information mailbox pointer 234 with the default address of the information mailbox. 235 The information mailbox pointer is not valid 236 until after the host receives the Init Complete interrupt from 237 the Wlan hardware. 238 ===============================================*/ 239 #define REG_EVENT_MAILBOX_PTR ( SCR_PAD1 ) 240 241 242 /*======================================================================= 243 Misc 244 ========================================================================*/ 245 246 247 #define REG_ENABLE_TX_RX ( IO_CONTROL_ENABLE ) 248 /* 249 * Rx configuration (filter) information element 250 * --------------------------------------------- 251 */ 252 #define REG_RX_CONFIG ( RX_CFG ) 253 #define REG_RX_FILTER ( RX_FILTER_CFG ) 254 255 #define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002 256 #define RX_CFG_PROMISCUOUS 0x0008 /* promiscuous - receives all valid frames */ 257 #define RX_CFG_BSSID 0x0020 /* receives frames from any BSSID */ 258 #define RX_CFG_MAC 0x0010 /* receives frames destined to any MAC address */ 259 #define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010 260 #define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000 261 #define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020 262 #define RX_CFG_ENABLE_ANY_BSSID 0x0000 263 #define RX_CFG_DISABLE_BCAST 0x0200 /* discards all broadcast frames */ 264 #define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400 265 #define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800 266 #define RX_CFG_COPY_RX_STATUS 0x2000 267 #define RX_CFG_TSF 0x10000 268 269 #define RX_CONFIG_OPTION_ANY_DST_MY_BSS ( RX_CFG_ENABLE_ANY_DEST_MAC | RX_CFG_ENABLE_ONLY_MY_BSSID) 270 #define RX_CONFIG_OPTION_MY_DST_ANY_BSS ( RX_CFG_ENABLE_ONLY_MY_DEST_MAC | RX_CFG_ENABLE_ANY_BSSID) 271 #define RX_CONFIG_OPTION_ANY_DST_ANY_BSS ( RX_CFG_ENABLE_ANY_DEST_MAC | RX_CFG_ENABLE_ANY_BSSID) 272 #define RX_CONFIG_OPTION_MY_DST_MY_BSS ( RX_CFG_ENABLE_ONLY_MY_DEST_MAC | RX_CFG_ENABLE_ONLY_MY_BSSID) 273 274 #define RX_CONFIG_OPTION_FOR_SCAN ( RX_CFG_ENABLE_PHY_HEADER_PLCP | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF) 275 #define RX_CONFIG_OPTION_FOR_MEASUREMENT ( RX_CFG_ENABLE_ANY_DEST_MAC ) 276 #define RX_CONFIG_OPTION_FOR_JOIN ( RX_CFG_ENABLE_ONLY_MY_BSSID | RX_CFG_ENABLE_ONLY_MY_DEST_MAC ) 277 #define RX_CONFIG_OPTION_FOR_IBSS_JOIN ( RX_CFG_ENABLE_ONLY_MY_SSID | RX_CFG_ENABLE_ONLY_MY_DEST_MAC ) 278 279 #define RX_FILTER_OPTION_DEF ( CFG_RX_MGMT_EN | CFG_RX_DATA_EN | CFG_RX_CTL_EN | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN) 280 #define RX_FILTER_OPTION_FILTER_ALL 0 281 #define RX_FILTER_OPTION_DEF_PRSP_BCN ( CFG_RX_PRSP_EN | CFG_RX_MGMT_EN | CFG_RX_CTL_EN | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN) 282 #define RX_FILTER_OPTION_JOIN ( CFG_RX_MGMT_EN | CFG_RX_DATA_EN | CFG_RX_CTL_EN | CFG_RX_BCN_EN | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN) 283 284 285 /*=============================================== 286 Phy regs 287 ===============================================*/ 288 #define ACX_PHY_ADDR_REG SBB_ADDR 289 #define ACX_PHY_DATA_REG SBB_DATA 290 #define ACX_PHY_CTRL_REG SBB_CTL 291 #define ACX_PHY_REG_WR_MASK 0x00000001ul 292 #define ACX_PHY_REG_RD_MASK 0x00000002ul 293 294 295 /*=============================================== 296 EEPROM Read/Write Request 32bit RW 297 ------------------------------------------ 298 1 EE_READ - EEPROM Read Request 1 - Setting this bit 299 loads a single byte of data into the EE_DATA 300 register from the EEPROM location specified in 301 the EE_ADDR register. 302 The Wlan hardware hardware clears this bit automatically. 303 EE_DATA is valid when this bit is cleared. 304 0 EE_WRITE - EEPROM Write Request - Setting this bit 305 writes a single byte of data from the EE_DATA register into the 306 EEPROM location specified in the EE_ADDR register. 307 The Wlan hardware hardware clears this bit automatically. 308 *===============================================*/ 309 #define ACX_EE_CTL_REG EE_CTL 310 #define EE_WRITE 0x00000001ul 311 #define EE_READ 0x00000002ul 312 313 /*=============================================== 314 EEPROM Address - 32bit RW 315 ------------------------------------------ 316 This register specifies the address 317 within the EEPROM from/to which to read/write data. 318 ===============================================*/ 319 #define ACX_EE_ADDR_REG EE_ADDR 320 321 /*=============================================== 322 EEPROM Data - 32bit RW 323 ------------------------------------------ 324 This register either holds the read 8 bits of 325 data from the EEPROM or the write data 326 to be written to the EEPROM. 327 ===============================================*/ 328 #define ACX_EE_DATA_REG EE_DATA 329 330 /*=============================================== 331 EEPROM Base Address - 32bit RW 332 ------------------------------------------ 333 This register holds the upper nine bits 334 [23:15] of the 24-bit Wlan hardware memory 335 address for burst reads from EEPROM accesses. 336 The EEPROM provides the lower 15 bits of this address. 337 The MSB of the address from the EEPROM is ignored. 338 ===============================================*/ 339 #define ACX_EE_CFG EE_CFG 340 341 /*=============================================== 342 GPIO Output Values -32bit, RW 343 ------------------------------------------ 344 [31:16] Reserved 345 [15: 0] Specify the output values (at the output driver inputs) for 346 GPIO[15:0], respectively. 347 ===============================================*/ 348 #define ACX_GPIO_OUT_REG GPIO_OUT 349 #define ACX_MAX_GPIO_LINES 15 350 351 /*=============================================== 352 Contention window -32bit, RW 353 ------------------------------------------ 354 [31:26] Reserved 355 [25:16] Max (0x3ff) 356 [15:07] Reserved 357 [06:00] Current contention window value - default is 0x1F 358 ===============================================*/ 359 #define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG 360 #define ACX_CONT_WIND_MIN_MASK 0x0000007f 361 #define ACX_CONT_WIND_MAX 0x03ff0000 362 363 /* 364 * Indirect slave register/memory registers 365 * ---------------------------------------- 366 */ 367 #define HW_SLAVE_REG_ADDR_REG 0x00000004 368 #define HW_SLAVE_REG_DATA_REG 0x00000008 369 #define HW_SLAVE_REG_CTRL_REG 0x0000000c 370 371 #define SLAVE_AUTO_INC 0x00010000 372 #define SLAVE_NO_AUTO_INC 0x00000000 373 #define SLAVE_HOST_LITTLE_ENDIAN 0x00000000 374 375 #define HW_SLAVE_MEM_ADDR_REG SLV_MEM_ADDR 376 #define HW_SLAVE_MEM_DATA_REG SLV_MEM_DATA 377 #define HW_SLAVE_MEM_CTRL_REG SLV_MEM_CTL 378 #define HW_SLAVE_MEM_ENDIAN_REG SLV_END_CTL 379 380 #define HW_FUNC_EVENT_INT_EN 0x8000 381 #define HW_FUNC_EVENT_MASK_REG 0x00000034 382 383 #define ACX_MAC_TIMESTAMP_REG (MAC_TIMESTAMP) 384 385 /*=============================================== 386 HI_CFG Interface Configuration Register Values 387 ------------------------------------------ 388 ===============================================*/ 389 #define HI_CFG_UART_ENABLE 0x00000004 390 #define HI_CFG_RST232_ENABLE 0x00000008 391 #define HI_CFG_CLOCK_REQ_SELECT 0x00000010 392 #define HI_CFG_HOST_INT_ENABLE 0x00000020 393 #define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040 394 #define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080 395 #define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100 396 #define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200 397 #define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400 398 399 /* 400 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile 401 * for platforms using active high interrupt level 402 */ 403 #ifdef USE_IRQ_ACTIVE_HIGH 404 #define HI_CFG_DEF_VAL \ 405 HI_CFG_UART_ENABLE | \ 406 HI_CFG_RST232_ENABLE | \ 407 HI_CFG_CLOCK_REQ_SELECT | \ 408 HI_CFG_HOST_INT_ENABLE 409 #else 410 #define HI_CFG_DEF_VAL \ 411 HI_CFG_UART_ENABLE | \ 412 HI_CFG_RST232_ENABLE | \ 413 HI_CFG_CLOCK_REQ_SELECT | \ 414 HI_CFG_HOST_INT_ENABLE | \ 415 HI_CFG_HOST_INT_ACTIVE_LOW 416 #endif 417 418 #endif /* DEVICE_H */ 419 420
