1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Pass to verify generated machine code. The following is checked: 11 // 12 // Operand counts: All explicit operands must be present. 13 // 14 // Register classes: All physical and virtual register operands must be 15 // compatible with the register class required by the instruction descriptor. 16 // 17 // Register live intervals: Registers must be defined only once, and must be 18 // defined before use. 19 // 20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the 21 // command-line option -verify-machineinstrs, or by defining the environment 22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive 23 // the verifier errors. 24 //===----------------------------------------------------------------------===// 25 26 #include "llvm/Instructions.h" 27 #include "llvm/Function.h" 28 #include "llvm/CodeGen/LiveIntervalAnalysis.h" 29 #include "llvm/CodeGen/LiveVariables.h" 30 #include "llvm/CodeGen/LiveStackAnalysis.h" 31 #include "llvm/CodeGen/MachineInstrBundle.h" 32 #include "llvm/CodeGen/MachineFunctionPass.h" 33 #include "llvm/CodeGen/MachineFrameInfo.h" 34 #include "llvm/CodeGen/MachineMemOperand.h" 35 #include "llvm/CodeGen/MachineRegisterInfo.h" 36 #include "llvm/CodeGen/Passes.h" 37 #include "llvm/MC/MCAsmInfo.h" 38 #include "llvm/Target/TargetMachine.h" 39 #include "llvm/Target/TargetRegisterInfo.h" 40 #include "llvm/Target/TargetInstrInfo.h" 41 #include "llvm/ADT/DenseSet.h" 42 #include "llvm/ADT/SetOperations.h" 43 #include "llvm/ADT/SmallVector.h" 44 #include "llvm/Support/Debug.h" 45 #include "llvm/Support/ErrorHandling.h" 46 #include "llvm/Support/raw_ostream.h" 47 using namespace llvm; 48 49 namespace { 50 struct MachineVerifier { 51 52 MachineVerifier(Pass *pass, const char *b) : 53 PASS(pass), 54 Banner(b), 55 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS")) 56 {} 57 58 bool runOnMachineFunction(MachineFunction &MF); 59 60 Pass *const PASS; 61 const char *Banner; 62 const char *const OutFileName; 63 raw_ostream *OS; 64 const MachineFunction *MF; 65 const TargetMachine *TM; 66 const TargetInstrInfo *TII; 67 const TargetRegisterInfo *TRI; 68 const MachineRegisterInfo *MRI; 69 70 unsigned foundErrors; 71 72 typedef SmallVector<unsigned, 16> RegVector; 73 typedef SmallVector<const uint32_t*, 4> RegMaskVector; 74 typedef DenseSet<unsigned> RegSet; 75 typedef DenseMap<unsigned, const MachineInstr*> RegMap; 76 77 const MachineInstr *FirstTerminator; 78 79 BitVector regsReserved; 80 BitVector regsAllocatable; 81 RegSet regsLive; 82 RegVector regsDefined, regsDead, regsKilled; 83 RegMaskVector regMasks; 84 RegSet regsLiveInButUnused; 85 86 SlotIndex lastIndex; 87 88 // Add Reg and any sub-registers to RV 89 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { 90 RV.push_back(Reg); 91 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 92 for (const uint16_t *R = TRI->getSubRegisters(Reg); *R; R++) 93 RV.push_back(*R); 94 } 95 96 struct BBInfo { 97 // Is this MBB reachable from the MF entry point? 98 bool reachable; 99 100 // Vregs that must be live in because they are used without being 101 // defined. Map value is the user. 102 RegMap vregsLiveIn; 103 104 // Regs killed in MBB. They may be defined again, and will then be in both 105 // regsKilled and regsLiveOut. 106 RegSet regsKilled; 107 108 // Regs defined in MBB and live out. Note that vregs passing through may 109 // be live out without being mentioned here. 110 RegSet regsLiveOut; 111 112 // Vregs that pass through MBB untouched. This set is disjoint from 113 // regsKilled and regsLiveOut. 114 RegSet vregsPassed; 115 116 // Vregs that must pass through MBB because they are needed by a successor 117 // block. This set is disjoint from regsLiveOut. 118 RegSet vregsRequired; 119 120 BBInfo() : reachable(false) {} 121 122 // Add register to vregsPassed if it belongs there. Return true if 123 // anything changed. 124 bool addPassed(unsigned Reg) { 125 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 126 return false; 127 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) 128 return false; 129 return vregsPassed.insert(Reg).second; 130 } 131 132 // Same for a full set. 133 bool addPassed(const RegSet &RS) { 134 bool changed = false; 135 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 136 if (addPassed(*I)) 137 changed = true; 138 return changed; 139 } 140 141 // Add register to vregsRequired if it belongs there. Return true if 142 // anything changed. 143 bool addRequired(unsigned Reg) { 144 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 145 return false; 146 if (regsLiveOut.count(Reg)) 147 return false; 148 return vregsRequired.insert(Reg).second; 149 } 150 151 // Same for a full set. 152 bool addRequired(const RegSet &RS) { 153 bool changed = false; 154 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 155 if (addRequired(*I)) 156 changed = true; 157 return changed; 158 } 159 160 // Same for a full map. 161 bool addRequired(const RegMap &RM) { 162 bool changed = false; 163 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I) 164 if (addRequired(I->first)) 165 changed = true; 166 return changed; 167 } 168 169 // Live-out registers are either in regsLiveOut or vregsPassed. 170 bool isLiveOut(unsigned Reg) const { 171 return regsLiveOut.count(Reg) || vregsPassed.count(Reg); 172 } 173 }; 174 175 // Extra register info per MBB. 176 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap; 177 178 bool isReserved(unsigned Reg) { 179 return Reg < regsReserved.size() && regsReserved.test(Reg); 180 } 181 182 bool isAllocatable(unsigned Reg) { 183 return Reg < regsAllocatable.size() && regsAllocatable.test(Reg); 184 } 185 186 // Analysis information if available 187 LiveVariables *LiveVars; 188 LiveIntervals *LiveInts; 189 LiveStacks *LiveStks; 190 SlotIndexes *Indexes; 191 192 void visitMachineFunctionBefore(); 193 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB); 194 void visitMachineInstrBefore(const MachineInstr *MI); 195 void visitMachineOperand(const MachineOperand *MO, unsigned MONum); 196 void visitMachineInstrAfter(const MachineInstr *MI); 197 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB); 198 void visitMachineFunctionAfter(); 199 200 void report(const char *msg, const MachineFunction *MF); 201 void report(const char *msg, const MachineBasicBlock *MBB); 202 void report(const char *msg, const MachineInstr *MI); 203 void report(const char *msg, const MachineOperand *MO, unsigned MONum); 204 205 void checkLiveness(const MachineOperand *MO, unsigned MONum); 206 void markReachable(const MachineBasicBlock *MBB); 207 void calcRegsPassed(); 208 void checkPHIOps(const MachineBasicBlock *MBB); 209 210 void calcRegsRequired(); 211 void verifyLiveVariables(); 212 void verifyLiveIntervals(); 213 }; 214 215 struct MachineVerifierPass : public MachineFunctionPass { 216 static char ID; // Pass ID, replacement for typeid 217 const char *const Banner; 218 219 MachineVerifierPass(const char *b = 0) 220 : MachineFunctionPass(ID), Banner(b) { 221 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry()); 222 } 223 224 void getAnalysisUsage(AnalysisUsage &AU) const { 225 AU.setPreservesAll(); 226 MachineFunctionPass::getAnalysisUsage(AU); 227 } 228 229 bool runOnMachineFunction(MachineFunction &MF) { 230 MF.verify(this, Banner); 231 return false; 232 } 233 }; 234 235 } 236 237 char MachineVerifierPass::ID = 0; 238 INITIALIZE_PASS(MachineVerifierPass, "machineverifier", 239 "Verify generated machine code", false, false) 240 241 FunctionPass *llvm::createMachineVerifierPass(const char *Banner) { 242 return new MachineVerifierPass(Banner); 243 } 244 245 void MachineFunction::verify(Pass *p, const char *Banner) const { 246 MachineVerifier(p, Banner) 247 .runOnMachineFunction(const_cast<MachineFunction&>(*this)); 248 } 249 250 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) { 251 raw_ostream *OutFile = 0; 252 if (OutFileName) { 253 std::string ErrorInfo; 254 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo, 255 raw_fd_ostream::F_Append); 256 if (!ErrorInfo.empty()) { 257 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n'; 258 exit(1); 259 } 260 261 OS = OutFile; 262 } else { 263 OS = &errs(); 264 } 265 266 foundErrors = 0; 267 268 this->MF = &MF; 269 TM = &MF.getTarget(); 270 TII = TM->getInstrInfo(); 271 TRI = TM->getRegisterInfo(); 272 MRI = &MF.getRegInfo(); 273 274 LiveVars = NULL; 275 LiveInts = NULL; 276 LiveStks = NULL; 277 Indexes = NULL; 278 if (PASS) { 279 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>(); 280 // We don't want to verify LiveVariables if LiveIntervals is available. 281 if (!LiveInts) 282 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>(); 283 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>(); 284 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>(); 285 } 286 287 visitMachineFunctionBefore(); 288 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end(); 289 MFI!=MFE; ++MFI) { 290 visitMachineBasicBlockBefore(MFI); 291 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(), 292 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) { 293 if (MBBI->getParent() != MFI) { 294 report("Bad instruction parent pointer", MFI); 295 *OS << "Instruction: " << *MBBI; 296 continue; 297 } 298 // Skip BUNDLE instruction for now. FIXME: We should add code to verify 299 // the BUNDLE's specifically. 300 if (MBBI->isBundle()) 301 continue; 302 visitMachineInstrBefore(MBBI); 303 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) 304 visitMachineOperand(&MBBI->getOperand(I), I); 305 visitMachineInstrAfter(MBBI); 306 } 307 visitMachineBasicBlockAfter(MFI); 308 } 309 visitMachineFunctionAfter(); 310 311 if (OutFile) 312 delete OutFile; 313 else if (foundErrors) 314 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors."); 315 316 // Clean up. 317 regsLive.clear(); 318 regsDefined.clear(); 319 regsDead.clear(); 320 regsKilled.clear(); 321 regMasks.clear(); 322 regsLiveInButUnused.clear(); 323 MBBInfoMap.clear(); 324 325 return false; // no changes 326 } 327 328 void MachineVerifier::report(const char *msg, const MachineFunction *MF) { 329 assert(MF); 330 *OS << '\n'; 331 if (!foundErrors++) { 332 if (Banner) 333 *OS << "# " << Banner << '\n'; 334 MF->print(*OS, Indexes); 335 } 336 *OS << "*** Bad machine code: " << msg << " ***\n" 337 << "- function: " << MF->getFunction()->getName() << "\n"; 338 } 339 340 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) { 341 assert(MBB); 342 report(msg, MBB->getParent()); 343 *OS << "- basic block: " << MBB->getName() 344 << " " << (void*)MBB 345 << " (BB#" << MBB->getNumber() << ")"; 346 if (Indexes) 347 *OS << " [" << Indexes->getMBBStartIdx(MBB) 348 << ';' << Indexes->getMBBEndIdx(MBB) << ')'; 349 *OS << '\n'; 350 } 351 352 void MachineVerifier::report(const char *msg, const MachineInstr *MI) { 353 assert(MI); 354 report(msg, MI->getParent()); 355 *OS << "- instruction: "; 356 if (Indexes && Indexes->hasIndex(MI)) 357 *OS << Indexes->getInstructionIndex(MI) << '\t'; 358 MI->print(*OS, TM); 359 } 360 361 void MachineVerifier::report(const char *msg, 362 const MachineOperand *MO, unsigned MONum) { 363 assert(MO); 364 report(msg, MO->getParent()); 365 *OS << "- operand " << MONum << ": "; 366 MO->print(*OS, TM); 367 *OS << "\n"; 368 } 369 370 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) { 371 BBInfo &MInfo = MBBInfoMap[MBB]; 372 if (!MInfo.reachable) { 373 MInfo.reachable = true; 374 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 375 SuE = MBB->succ_end(); SuI != SuE; ++SuI) 376 markReachable(*SuI); 377 } 378 } 379 380 void MachineVerifier::visitMachineFunctionBefore() { 381 lastIndex = SlotIndex(); 382 regsReserved = TRI->getReservedRegs(*MF); 383 384 // A sub-register of a reserved register is also reserved 385 for (int Reg = regsReserved.find_first(); Reg>=0; 386 Reg = regsReserved.find_next(Reg)) { 387 for (const uint16_t *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) { 388 // FIXME: This should probably be: 389 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register"); 390 regsReserved.set(*Sub); 391 } 392 } 393 394 regsAllocatable = TRI->getAllocatableSet(*MF); 395 396 markReachable(&MF->front()); 397 } 398 399 // Does iterator point to a and b as the first two elements? 400 static bool matchPair(MachineBasicBlock::const_succ_iterator i, 401 const MachineBasicBlock *a, const MachineBasicBlock *b) { 402 if (*i == a) 403 return *++i == b; 404 if (*i == b) 405 return *++i == a; 406 return false; 407 } 408 409 void 410 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { 411 FirstTerminator = 0; 412 413 if (MRI->isSSA()) { 414 // If this block has allocatable physical registers live-in, check that 415 // it is an entry block or landing pad. 416 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(), 417 LE = MBB->livein_end(); 418 LI != LE; ++LI) { 419 unsigned reg = *LI; 420 if (isAllocatable(reg) && !MBB->isLandingPad() && 421 MBB != MBB->getParent()->begin()) { 422 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB); 423 } 424 } 425 } 426 427 // Count the number of landing pad successors. 428 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs; 429 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(), 430 E = MBB->succ_end(); I != E; ++I) { 431 if ((*I)->isLandingPad()) 432 LandingPadSuccs.insert(*I); 433 } 434 435 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo(); 436 const BasicBlock *BB = MBB->getBasicBlock(); 437 if (LandingPadSuccs.size() > 1 && 438 !(AsmInfo && 439 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj && 440 BB && isa<SwitchInst>(BB->getTerminator()))) 441 report("MBB has more than one landing pad successor", MBB); 442 443 // Call AnalyzeBranch. If it succeeds, there several more conditions to check. 444 MachineBasicBlock *TBB = 0, *FBB = 0; 445 SmallVector<MachineOperand, 4> Cond; 446 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB), 447 TBB, FBB, Cond)) { 448 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's 449 // check whether its answers match up with reality. 450 if (!TBB && !FBB) { 451 // Block falls through to its successor. 452 MachineFunction::const_iterator MBBI = MBB; 453 ++MBBI; 454 if (MBBI == MF->end()) { 455 // It's possible that the block legitimately ends with a noreturn 456 // call or an unreachable, in which case it won't actually fall 457 // out the bottom of the function. 458 } else if (MBB->succ_size() == LandingPadSuccs.size()) { 459 // It's possible that the block legitimately ends with a noreturn 460 // call or an unreachable, in which case it won't actuall fall 461 // out of the block. 462 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) { 463 report("MBB exits via unconditional fall-through but doesn't have " 464 "exactly one CFG successor!", MBB); 465 } else if (!MBB->isSuccessor(MBBI)) { 466 report("MBB exits via unconditional fall-through but its successor " 467 "differs from its CFG successor!", MBB); 468 } 469 if (!MBB->empty() && MBB->back().isBarrier() && 470 !TII->isPredicated(&MBB->back())) { 471 report("MBB exits via unconditional fall-through but ends with a " 472 "barrier instruction!", MBB); 473 } 474 if (!Cond.empty()) { 475 report("MBB exits via unconditional fall-through but has a condition!", 476 MBB); 477 } 478 } else if (TBB && !FBB && Cond.empty()) { 479 // Block unconditionally branches somewhere. 480 if (MBB->succ_size() != 1+LandingPadSuccs.size()) { 481 report("MBB exits via unconditional branch but doesn't have " 482 "exactly one CFG successor!", MBB); 483 } else if (!MBB->isSuccessor(TBB)) { 484 report("MBB exits via unconditional branch but the CFG " 485 "successor doesn't match the actual successor!", MBB); 486 } 487 if (MBB->empty()) { 488 report("MBB exits via unconditional branch but doesn't contain " 489 "any instructions!", MBB); 490 } else if (!MBB->back().isBarrier()) { 491 report("MBB exits via unconditional branch but doesn't end with a " 492 "barrier instruction!", MBB); 493 } else if (!MBB->back().isTerminator()) { 494 report("MBB exits via unconditional branch but the branch isn't a " 495 "terminator instruction!", MBB); 496 } 497 } else if (TBB && !FBB && !Cond.empty()) { 498 // Block conditionally branches somewhere, otherwise falls through. 499 MachineFunction::const_iterator MBBI = MBB; 500 ++MBBI; 501 if (MBBI == MF->end()) { 502 report("MBB conditionally falls through out of function!", MBB); 503 } if (MBB->succ_size() != 2) { 504 report("MBB exits via conditional branch/fall-through but doesn't have " 505 "exactly two CFG successors!", MBB); 506 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) { 507 report("MBB exits via conditional branch/fall-through but the CFG " 508 "successors don't match the actual successors!", MBB); 509 } 510 if (MBB->empty()) { 511 report("MBB exits via conditional branch/fall-through but doesn't " 512 "contain any instructions!", MBB); 513 } else if (MBB->back().isBarrier()) { 514 report("MBB exits via conditional branch/fall-through but ends with a " 515 "barrier instruction!", MBB); 516 } else if (!MBB->back().isTerminator()) { 517 report("MBB exits via conditional branch/fall-through but the branch " 518 "isn't a terminator instruction!", MBB); 519 } 520 } else if (TBB && FBB) { 521 // Block conditionally branches somewhere, otherwise branches 522 // somewhere else. 523 if (MBB->succ_size() != 2) { 524 report("MBB exits via conditional branch/branch but doesn't have " 525 "exactly two CFG successors!", MBB); 526 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) { 527 report("MBB exits via conditional branch/branch but the CFG " 528 "successors don't match the actual successors!", MBB); 529 } 530 if (MBB->empty()) { 531 report("MBB exits via conditional branch/branch but doesn't " 532 "contain any instructions!", MBB); 533 } else if (!MBB->back().isBarrier()) { 534 report("MBB exits via conditional branch/branch but doesn't end with a " 535 "barrier instruction!", MBB); 536 } else if (!MBB->back().isTerminator()) { 537 report("MBB exits via conditional branch/branch but the branch " 538 "isn't a terminator instruction!", MBB); 539 } 540 if (Cond.empty()) { 541 report("MBB exits via conditinal branch/branch but there's no " 542 "condition!", MBB); 543 } 544 } else { 545 report("AnalyzeBranch returned invalid data!", MBB); 546 } 547 } 548 549 regsLive.clear(); 550 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 551 E = MBB->livein_end(); I != E; ++I) { 552 if (!TargetRegisterInfo::isPhysicalRegister(*I)) { 553 report("MBB live-in list contains non-physical register", MBB); 554 continue; 555 } 556 regsLive.insert(*I); 557 for (const uint16_t *R = TRI->getSubRegisters(*I); *R; R++) 558 regsLive.insert(*R); 559 } 560 regsLiveInButUnused = regsLive; 561 562 const MachineFrameInfo *MFI = MF->getFrameInfo(); 563 assert(MFI && "Function has no frame info"); 564 BitVector PR = MFI->getPristineRegs(MBB); 565 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) { 566 regsLive.insert(I); 567 for (const uint16_t *R = TRI->getSubRegisters(I); *R; R++) 568 regsLive.insert(*R); 569 } 570 571 regsKilled.clear(); 572 regsDefined.clear(); 573 574 if (Indexes) 575 lastIndex = Indexes->getMBBStartIdx(MBB); 576 } 577 578 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { 579 const MCInstrDesc &MCID = MI->getDesc(); 580 if (MI->getNumOperands() < MCID.getNumOperands()) { 581 report("Too few operands", MI); 582 *OS << MCID.getNumOperands() << " operands expected, but " 583 << MI->getNumExplicitOperands() << " given.\n"; 584 } 585 586 // Check the MachineMemOperands for basic consistency. 587 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 588 E = MI->memoperands_end(); I != E; ++I) { 589 if ((*I)->isLoad() && !MI->mayLoad()) 590 report("Missing mayLoad flag", MI); 591 if ((*I)->isStore() && !MI->mayStore()) 592 report("Missing mayStore flag", MI); 593 } 594 595 // Debug values must not have a slot index. 596 // Other instructions must have one, unless they are inside a bundle. 597 if (LiveInts) { 598 bool mapped = !LiveInts->isNotInMIMap(MI); 599 if (MI->isDebugValue()) { 600 if (mapped) 601 report("Debug instruction has a slot index", MI); 602 } else if (MI->isInsideBundle()) { 603 if (mapped) 604 report("Instruction inside bundle has a slot index", MI); 605 } else { 606 if (!mapped) 607 report("Missing slot index", MI); 608 } 609 } 610 611 // Ensure non-terminators don't follow terminators. 612 // Ignore predicated terminators formed by if conversion. 613 // FIXME: If conversion shouldn't need to violate this rule. 614 if (MI->isTerminator() && !TII->isPredicated(MI)) { 615 if (!FirstTerminator) 616 FirstTerminator = MI; 617 } else if (FirstTerminator) { 618 report("Non-terminator instruction after the first terminator", MI); 619 *OS << "First terminator was:\t" << *FirstTerminator; 620 } 621 622 StringRef ErrorInfo; 623 if (!TII->verifyInstruction(MI, ErrorInfo)) 624 report(ErrorInfo.data(), MI); 625 } 626 627 void 628 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { 629 const MachineInstr *MI = MO->getParent(); 630 const MCInstrDesc &MCID = MI->getDesc(); 631 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; 632 633 // The first MCID.NumDefs operands must be explicit register defines 634 if (MONum < MCID.getNumDefs()) { 635 if (!MO->isReg()) 636 report("Explicit definition must be a register", MO, MONum); 637 else if (!MO->isDef()) 638 report("Explicit definition marked as use", MO, MONum); 639 else if (MO->isImplicit()) 640 report("Explicit definition marked as implicit", MO, MONum); 641 } else if (MONum < MCID.getNumOperands()) { 642 // Don't check if it's the last operand in a variadic instruction. See, 643 // e.g., LDM_RET in the arm back end. 644 if (MO->isReg() && 645 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) { 646 if (MO->isDef() && !MCOI.isOptionalDef()) 647 report("Explicit operand marked as def", MO, MONum); 648 if (MO->isImplicit()) 649 report("Explicit operand marked as implicit", MO, MONum); 650 } 651 } else { 652 // ARM adds %reg0 operands to indicate predicates. We'll allow that. 653 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg()) 654 report("Extra explicit operand on non-variadic instruction", MO, MONum); 655 } 656 657 switch (MO->getType()) { 658 case MachineOperand::MO_Register: { 659 const unsigned Reg = MO->getReg(); 660 if (!Reg) 661 return; 662 if (MRI->tracksLiveness() && !MI->isDebugValue()) 663 checkLiveness(MO, MONum); 664 665 666 // Check register classes. 667 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) { 668 unsigned SubIdx = MO->getSubReg(); 669 670 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 671 if (SubIdx) { 672 report("Illegal subregister index for physical register", MO, MONum); 673 return; 674 } 675 if (const TargetRegisterClass *DRC = TII->getRegClass(MCID,MONum,TRI)) { 676 if (!DRC->contains(Reg)) { 677 report("Illegal physical register for instruction", MO, MONum); 678 *OS << TRI->getName(Reg) << " is not a " 679 << DRC->getName() << " register.\n"; 680 } 681 } 682 } else { 683 // Virtual register. 684 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 685 if (SubIdx) { 686 const TargetRegisterClass *SRC = 687 TRI->getSubClassWithSubReg(RC, SubIdx); 688 if (!SRC) { 689 report("Invalid subregister index for virtual register", MO, MONum); 690 *OS << "Register class " << RC->getName() 691 << " does not support subreg index " << SubIdx << "\n"; 692 return; 693 } 694 if (RC != SRC) { 695 report("Invalid register class for subregister index", MO, MONum); 696 *OS << "Register class " << RC->getName() 697 << " does not fully support subreg index " << SubIdx << "\n"; 698 return; 699 } 700 } 701 if (const TargetRegisterClass *DRC = TII->getRegClass(MCID,MONum,TRI)) { 702 if (SubIdx) { 703 const TargetRegisterClass *SuperRC = 704 TRI->getLargestLegalSuperClass(RC); 705 if (!SuperRC) { 706 report("No largest legal super class exists.", MO, MONum); 707 return; 708 } 709 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); 710 if (!DRC) { 711 report("No matching super-reg register class.", MO, MONum); 712 return; 713 } 714 } 715 if (!RC->hasSuperClassEq(DRC)) { 716 report("Illegal virtual register for instruction", MO, MONum); 717 *OS << "Expected a " << DRC->getName() << " register, but got a " 718 << RC->getName() << " register\n"; 719 } 720 } 721 } 722 } 723 break; 724 } 725 726 case MachineOperand::MO_RegisterMask: 727 regMasks.push_back(MO->getRegMask()); 728 break; 729 730 case MachineOperand::MO_MachineBasicBlock: 731 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent())) 732 report("PHI operand is not in the CFG", MO, MONum); 733 break; 734 735 case MachineOperand::MO_FrameIndex: 736 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && 737 LiveInts && !LiveInts->isNotInMIMap(MI)) { 738 LiveInterval &LI = LiveStks->getInterval(MO->getIndex()); 739 SlotIndex Idx = LiveInts->getInstructionIndex(MI); 740 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) { 741 report("Instruction loads from dead spill slot", MO, MONum); 742 *OS << "Live stack: " << LI << '\n'; 743 } 744 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) { 745 report("Instruction stores to dead spill slot", MO, MONum); 746 *OS << "Live stack: " << LI << '\n'; 747 } 748 } 749 break; 750 751 default: 752 break; 753 } 754 } 755 756 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) { 757 const MachineInstr *MI = MO->getParent(); 758 const unsigned Reg = MO->getReg(); 759 760 // Both use and def operands can read a register. 761 if (MO->readsReg()) { 762 regsLiveInButUnused.erase(Reg); 763 764 bool isKill = false; 765 unsigned defIdx; 766 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) { 767 // A two-addr use counts as a kill if use and def are the same. 768 unsigned DefReg = MI->getOperand(defIdx).getReg(); 769 if (Reg == DefReg) 770 isKill = true; 771 else if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 772 report("Two-address instruction operands must be identical", MO, MONum); 773 } 774 } else 775 isKill = MO->isKill(); 776 777 if (isKill) 778 addRegWithSubRegs(regsKilled, Reg); 779 780 // Check that LiveVars knows this kill. 781 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) && 782 MO->isKill()) { 783 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); 784 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end()) 785 report("Kill missing from LiveVariables", MO, MONum); 786 } 787 788 // Check LiveInts liveness and kill. 789 if (TargetRegisterInfo::isVirtualRegister(Reg) && 790 LiveInts && !LiveInts->isNotInMIMap(MI)) { 791 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getRegSlot(true); 792 if (LiveInts->hasInterval(Reg)) { 793 const LiveInterval &LI = LiveInts->getInterval(Reg); 794 if (!LI.liveAt(UseIdx)) { 795 report("No live range at use", MO, MONum); 796 *OS << UseIdx << " is not live in " << LI << '\n'; 797 } 798 // Check for extra kill flags. 799 // Note that we allow missing kill flags for now. 800 if (MO->isKill() && !LI.killedAt(UseIdx.getRegSlot())) { 801 report("Live range continues after kill flag", MO, MONum); 802 *OS << "Live range: " << LI << '\n'; 803 } 804 } else { 805 report("Virtual register has no Live interval", MO, MONum); 806 } 807 } 808 809 // Use of a dead register. 810 if (!regsLive.count(Reg)) { 811 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 812 // Reserved registers may be used even when 'dead'. 813 if (!isReserved(Reg)) 814 report("Using an undefined physical register", MO, MONum); 815 } else { 816 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 817 // We don't know which virtual registers are live in, so only complain 818 // if vreg was killed in this MBB. Otherwise keep track of vregs that 819 // must be live in. PHI instructions are handled separately. 820 if (MInfo.regsKilled.count(Reg)) 821 report("Using a killed virtual register", MO, MONum); 822 else if (!MI->isPHI()) 823 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI)); 824 } 825 } 826 } 827 828 if (MO->isDef()) { 829 // Register defined. 830 // TODO: verify that earlyclobber ops are not used. 831 if (MO->isDead()) 832 addRegWithSubRegs(regsDead, Reg); 833 else 834 addRegWithSubRegs(regsDefined, Reg); 835 836 // Verify SSA form. 837 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) && 838 llvm::next(MRI->def_begin(Reg)) != MRI->def_end()) 839 report("Multiple virtual register defs in SSA form", MO, MONum); 840 841 // Check LiveInts for a live range, but only for virtual registers. 842 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) && 843 !LiveInts->isNotInMIMap(MI)) { 844 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getRegSlot(); 845 if (LiveInts->hasInterval(Reg)) { 846 const LiveInterval &LI = LiveInts->getInterval(Reg); 847 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { 848 assert(VNI && "NULL valno is not allowed"); 849 if (VNI->def != DefIdx && !MO->isEarlyClobber()) { 850 report("Inconsistent valno->def", MO, MONum); 851 *OS << "Valno " << VNI->id << " is not defined at " 852 << DefIdx << " in " << LI << '\n'; 853 } 854 } else { 855 report("No live range at def", MO, MONum); 856 *OS << DefIdx << " is not live in " << LI << '\n'; 857 } 858 } else { 859 report("Virtual register has no Live interval", MO, MONum); 860 } 861 } 862 } 863 } 864 865 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) { 866 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 867 set_union(MInfo.regsKilled, regsKilled); 868 set_subtract(regsLive, regsKilled); regsKilled.clear(); 869 // Kill any masked registers. 870 while (!regMasks.empty()) { 871 const uint32_t *Mask = regMasks.pop_back_val(); 872 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I) 873 if (TargetRegisterInfo::isPhysicalRegister(*I) && 874 MachineOperand::clobbersPhysReg(Mask, *I)) 875 regsDead.push_back(*I); 876 } 877 set_subtract(regsLive, regsDead); regsDead.clear(); 878 set_union(regsLive, regsDefined); regsDefined.clear(); 879 880 if (Indexes && Indexes->hasIndex(MI)) { 881 SlotIndex idx = Indexes->getInstructionIndex(MI); 882 if (!(idx > lastIndex)) { 883 report("Instruction index out of order", MI); 884 *OS << "Last instruction was at " << lastIndex << '\n'; 885 } 886 lastIndex = idx; 887 } 888 } 889 890 void 891 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) { 892 MBBInfoMap[MBB].regsLiveOut = regsLive; 893 regsLive.clear(); 894 895 if (Indexes) { 896 SlotIndex stop = Indexes->getMBBEndIdx(MBB); 897 if (!(stop > lastIndex)) { 898 report("Block ends before last instruction index", MBB); 899 *OS << "Block ends at " << stop 900 << " last instruction was at " << lastIndex << '\n'; 901 } 902 lastIndex = stop; 903 } 904 } 905 906 // Calculate the largest possible vregsPassed sets. These are the registers that 907 // can pass through an MBB live, but may not be live every time. It is assumed 908 // that all vregsPassed sets are empty before the call. 909 void MachineVerifier::calcRegsPassed() { 910 // First push live-out regs to successors' vregsPassed. Remember the MBBs that 911 // have any vregsPassed. 912 SmallPtrSet<const MachineBasicBlock*, 8> todo; 913 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 914 MFI != MFE; ++MFI) { 915 const MachineBasicBlock &MBB(*MFI); 916 BBInfo &MInfo = MBBInfoMap[&MBB]; 917 if (!MInfo.reachable) 918 continue; 919 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(), 920 SuE = MBB.succ_end(); SuI != SuE; ++SuI) { 921 BBInfo &SInfo = MBBInfoMap[*SuI]; 922 if (SInfo.addPassed(MInfo.regsLiveOut)) 923 todo.insert(*SuI); 924 } 925 } 926 927 // Iteratively push vregsPassed to successors. This will converge to the same 928 // final state regardless of DenseSet iteration order. 929 while (!todo.empty()) { 930 const MachineBasicBlock *MBB = *todo.begin(); 931 todo.erase(MBB); 932 BBInfo &MInfo = MBBInfoMap[MBB]; 933 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 934 SuE = MBB->succ_end(); SuI != SuE; ++SuI) { 935 if (*SuI == MBB) 936 continue; 937 BBInfo &SInfo = MBBInfoMap[*SuI]; 938 if (SInfo.addPassed(MInfo.vregsPassed)) 939 todo.insert(*SuI); 940 } 941 } 942 } 943 944 // Calculate the set of virtual registers that must be passed through each basic 945 // block in order to satisfy the requirements of successor blocks. This is very 946 // similar to calcRegsPassed, only backwards. 947 void MachineVerifier::calcRegsRequired() { 948 // First push live-in regs to predecessors' vregsRequired. 949 SmallPtrSet<const MachineBasicBlock*, 8> todo; 950 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 951 MFI != MFE; ++MFI) { 952 const MachineBasicBlock &MBB(*MFI); 953 BBInfo &MInfo = MBBInfoMap[&MBB]; 954 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(), 955 PrE = MBB.pred_end(); PrI != PrE; ++PrI) { 956 BBInfo &PInfo = MBBInfoMap[*PrI]; 957 if (PInfo.addRequired(MInfo.vregsLiveIn)) 958 todo.insert(*PrI); 959 } 960 } 961 962 // Iteratively push vregsRequired to predecessors. This will converge to the 963 // same final state regardless of DenseSet iteration order. 964 while (!todo.empty()) { 965 const MachineBasicBlock *MBB = *todo.begin(); 966 todo.erase(MBB); 967 BBInfo &MInfo = MBBInfoMap[MBB]; 968 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 969 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 970 if (*PrI == MBB) 971 continue; 972 BBInfo &SInfo = MBBInfoMap[*PrI]; 973 if (SInfo.addRequired(MInfo.vregsRequired)) 974 todo.insert(*PrI); 975 } 976 } 977 } 978 979 // Check PHI instructions at the beginning of MBB. It is assumed that 980 // calcRegsPassed has been run so BBInfo::isLiveOut is valid. 981 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) { 982 SmallPtrSet<const MachineBasicBlock*, 8> seen; 983 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end(); 984 BBI != BBE && BBI->isPHI(); ++BBI) { 985 seen.clear(); 986 987 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 988 unsigned Reg = BBI->getOperand(i).getReg(); 989 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB(); 990 if (!Pre->isSuccessor(MBB)) 991 continue; 992 seen.insert(Pre); 993 BBInfo &PrInfo = MBBInfoMap[Pre]; 994 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg)) 995 report("PHI operand is not live-out from predecessor", 996 &BBI->getOperand(i), i); 997 } 998 999 // Did we see all predecessors? 1000 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 1001 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 1002 if (!seen.count(*PrI)) { 1003 report("Missing PHI operand", BBI); 1004 *OS << "BB#" << (*PrI)->getNumber() 1005 << " is a predecessor according to the CFG.\n"; 1006 } 1007 } 1008 } 1009 } 1010 1011 void MachineVerifier::visitMachineFunctionAfter() { 1012 calcRegsPassed(); 1013 1014 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1015 MFI != MFE; ++MFI) { 1016 BBInfo &MInfo = MBBInfoMap[MFI]; 1017 1018 // Skip unreachable MBBs. 1019 if (!MInfo.reachable) 1020 continue; 1021 1022 checkPHIOps(MFI); 1023 } 1024 1025 // Now check liveness info if available 1026 calcRegsRequired(); 1027 1028 if (MRI->isSSA() && !MF->empty()) { 1029 BBInfo &MInfo = MBBInfoMap[&MF->front()]; 1030 for (RegSet::iterator 1031 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E; 1032 ++I) 1033 report("Virtual register def doesn't dominate all uses.", 1034 MRI->getVRegDef(*I)); 1035 } 1036 1037 if (LiveVars) 1038 verifyLiveVariables(); 1039 if (LiveInts) 1040 verifyLiveIntervals(); 1041 } 1042 1043 void MachineVerifier::verifyLiveVariables() { 1044 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars"); 1045 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 1046 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 1047 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); 1048 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1049 MFI != MFE; ++MFI) { 1050 BBInfo &MInfo = MBBInfoMap[MFI]; 1051 1052 // Our vregsRequired should be identical to LiveVariables' AliveBlocks 1053 if (MInfo.vregsRequired.count(Reg)) { 1054 if (!VI.AliveBlocks.test(MFI->getNumber())) { 1055 report("LiveVariables: Block missing from AliveBlocks", MFI); 1056 *OS << "Virtual register " << PrintReg(Reg) 1057 << " must be live through the block.\n"; 1058 } 1059 } else { 1060 if (VI.AliveBlocks.test(MFI->getNumber())) { 1061 report("LiveVariables: Block should not be in AliveBlocks", MFI); 1062 *OS << "Virtual register " << PrintReg(Reg) 1063 << " is not needed live through the block.\n"; 1064 } 1065 } 1066 } 1067 } 1068 } 1069 1070 void MachineVerifier::verifyLiveIntervals() { 1071 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts"); 1072 for (LiveIntervals::const_iterator LVI = LiveInts->begin(), 1073 LVE = LiveInts->end(); LVI != LVE; ++LVI) { 1074 const LiveInterval &LI = *LVI->second; 1075 1076 // Spilling and splitting may leave unused registers around. Skip them. 1077 if (MRI->use_empty(LI.reg)) 1078 continue; 1079 1080 // Physical registers have much weirdness going on, mostly from coalescing. 1081 // We should probably fix it, but for now just ignore them. 1082 if (TargetRegisterInfo::isPhysicalRegister(LI.reg)) 1083 continue; 1084 1085 assert(LVI->first == LI.reg && "Invalid reg to interval mapping"); 1086 1087 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end(); 1088 I!=E; ++I) { 1089 VNInfo *VNI = *I; 1090 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def); 1091 1092 if (!DefVNI) { 1093 if (!VNI->isUnused()) { 1094 report("Valno not live at def and not marked unused", MF); 1095 *OS << "Valno #" << VNI->id << " in " << LI << '\n'; 1096 } 1097 continue; 1098 } 1099 1100 if (VNI->isUnused()) 1101 continue; 1102 1103 if (DefVNI != VNI) { 1104 report("Live range at def has different valno", MF); 1105 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1106 << " where valno #" << DefVNI->id << " is live in " << LI << '\n'; 1107 continue; 1108 } 1109 1110 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def); 1111 if (!MBB) { 1112 report("Invalid definition index", MF); 1113 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1114 << " in " << LI << '\n'; 1115 continue; 1116 } 1117 1118 if (VNI->isPHIDef()) { 1119 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) { 1120 report("PHIDef value is not defined at MBB start", MF); 1121 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1122 << ", not at the beginning of BB#" << MBB->getNumber() 1123 << " in " << LI << '\n'; 1124 } 1125 } else { 1126 // Non-PHI def. 1127 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def); 1128 if (!MI) { 1129 report("No instruction at def index", MF); 1130 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1131 << " in " << LI << '\n'; 1132 continue; 1133 } 1134 1135 bool hasDef = false; 1136 bool isEarlyClobber = false; 1137 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) { 1138 if (!MOI->isReg() || !MOI->isDef()) 1139 continue; 1140 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { 1141 if (MOI->getReg() != LI.reg) 1142 continue; 1143 } else { 1144 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) || 1145 !TRI->regsOverlap(LI.reg, MOI->getReg())) 1146 continue; 1147 } 1148 hasDef = true; 1149 if (MOI->isEarlyClobber()) 1150 isEarlyClobber = true; 1151 } 1152 1153 if (!hasDef) { 1154 report("Defining instruction does not modify register", MI); 1155 *OS << "Valno #" << VNI->id << " in " << LI << '\n'; 1156 } 1157 1158 // Early clobber defs begin at USE slots, but other defs must begin at 1159 // DEF slots. 1160 if (isEarlyClobber) { 1161 if (!VNI->def.isEarlyClobber()) { 1162 report("Early clobber def must be at an early-clobber slot", MF); 1163 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1164 << " in " << LI << '\n'; 1165 } 1166 } else if (!VNI->def.isRegister()) { 1167 report("Non-PHI, non-early clobber def must be at a register slot", 1168 MF); 1169 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1170 << " in " << LI << '\n'; 1171 } 1172 } 1173 } 1174 1175 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) { 1176 const VNInfo *VNI = I->valno; 1177 assert(VNI && "Live range has no valno"); 1178 1179 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) { 1180 report("Foreign valno in live range", MF); 1181 I->print(*OS); 1182 *OS << " has a valno not in " << LI << '\n'; 1183 } 1184 1185 if (VNI->isUnused()) { 1186 report("Live range valno is marked unused", MF); 1187 I->print(*OS); 1188 *OS << " in " << LI << '\n'; 1189 } 1190 1191 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start); 1192 if (!MBB) { 1193 report("Bad start of live segment, no basic block", MF); 1194 I->print(*OS); 1195 *OS << " in " << LI << '\n'; 1196 continue; 1197 } 1198 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB); 1199 if (I->start != MBBStartIdx && I->start != VNI->def) { 1200 report("Live segment must begin at MBB entry or valno def", MBB); 1201 I->print(*OS); 1202 *OS << " in " << LI << '\n' << "Basic block starts at " 1203 << MBBStartIdx << '\n'; 1204 } 1205 1206 const MachineBasicBlock *EndMBB = 1207 LiveInts->getMBBFromIndex(I->end.getPrevSlot()); 1208 if (!EndMBB) { 1209 report("Bad end of live segment, no basic block", MF); 1210 I->print(*OS); 1211 *OS << " in " << LI << '\n'; 1212 continue; 1213 } 1214 1215 // No more checks for live-out segments. 1216 if (I->end == LiveInts->getMBBEndIdx(EndMBB)) 1217 continue; 1218 1219 // The live segment is ending inside EndMBB 1220 const MachineInstr *MI = 1221 LiveInts->getInstructionFromIndex(I->end.getPrevSlot()); 1222 if (!MI) { 1223 report("Live segment doesn't end at a valid instruction", EndMBB); 1224 I->print(*OS); 1225 *OS << " in " << LI << '\n' << "Basic block starts at " 1226 << MBBStartIdx << '\n'; 1227 continue; 1228 } 1229 1230 // The block slot must refer to a basic block boundary. 1231 if (I->end.isBlock()) { 1232 report("Live segment ends at B slot of an instruction", MI); 1233 I->print(*OS); 1234 *OS << " in " << LI << '\n'; 1235 } 1236 1237 if (I->end.isDead()) { 1238 // Segment ends on the dead slot. 1239 // That means there must be a dead def. 1240 if (!SlotIndex::isSameInstr(I->start, I->end)) { 1241 report("Live segment ending at dead slot spans instructions", MI); 1242 I->print(*OS); 1243 *OS << " in " << LI << '\n'; 1244 } 1245 } 1246 1247 // A live segment can only end at an early-clobber slot if it is being 1248 // redefined by an early-clobber def. 1249 if (I->end.isEarlyClobber()) { 1250 if (I+1 == E || (I+1)->start != I->end) { 1251 report("Live segment ending at early clobber slot must be " 1252 "redefined by an EC def in the same instruction", MI); 1253 I->print(*OS); 1254 *OS << " in " << LI << '\n'; 1255 } 1256 } 1257 1258 // The following checks only apply to virtual registers. Physreg liveness 1259 // is too weird to check. 1260 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { 1261 // A live range can end with either a redefinition, a kill flag on a 1262 // use, or a dead flag on a def. 1263 bool hasRead = false; 1264 bool hasDeadDef = false; 1265 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) { 1266 if (!MOI->isReg() || MOI->getReg() != LI.reg) 1267 continue; 1268 if (MOI->readsReg()) 1269 hasRead = true; 1270 if (MOI->isDef() && MOI->isDead()) 1271 hasDeadDef = true; 1272 } 1273 1274 if (I->end.isDead()) { 1275 if (!hasDeadDef) { 1276 report("Instruction doesn't have a dead def operand", MI); 1277 I->print(*OS); 1278 *OS << " in " << LI << '\n'; 1279 } 1280 } else { 1281 if (!hasRead) { 1282 report("Instruction ending live range doesn't read the register", 1283 MI); 1284 I->print(*OS); 1285 *OS << " in " << LI << '\n'; 1286 } 1287 } 1288 } 1289 1290 // Now check all the basic blocks in this live segment. 1291 MachineFunction::const_iterator MFI = MBB; 1292 // Is this live range the beginning of a non-PHIDef VN? 1293 if (I->start == VNI->def && !VNI->isPHIDef()) { 1294 // Not live-in to any blocks. 1295 if (MBB == EndMBB) 1296 continue; 1297 // Skip this block. 1298 ++MFI; 1299 } 1300 for (;;) { 1301 assert(LiveInts->isLiveInToMBB(LI, MFI)); 1302 // We don't know how to track physregs into a landing pad. 1303 if (TargetRegisterInfo::isPhysicalRegister(LI.reg) && 1304 MFI->isLandingPad()) { 1305 if (&*MFI == EndMBB) 1306 break; 1307 ++MFI; 1308 continue; 1309 } 1310 // Check that VNI is live-out of all predecessors. 1311 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(), 1312 PE = MFI->pred_end(); PI != PE; ++PI) { 1313 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI); 1314 const VNInfo *PVNI = LI.getVNInfoBefore(PEnd); 1315 1316 if (VNI->isPHIDef() && VNI->def == LiveInts->getMBBStartIdx(MFI)) 1317 continue; 1318 1319 if (!PVNI) { 1320 report("Register not marked live out of predecessor", *PI); 1321 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber() 1322 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before " 1323 << PEnd << " in " << LI << '\n'; 1324 continue; 1325 } 1326 1327 if (PVNI != VNI) { 1328 report("Different value live out of predecessor", *PI); 1329 *OS << "Valno #" << PVNI->id << " live out of BB#" 1330 << (*PI)->getNumber() << '@' << PEnd 1331 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber() 1332 << '@' << LiveInts->getMBBStartIdx(MFI) << " in " << LI << '\n'; 1333 } 1334 } 1335 if (&*MFI == EndMBB) 1336 break; 1337 ++MFI; 1338 } 1339 } 1340 1341 // Check the LI only has one connected component. 1342 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { 1343 ConnectedVNInfoEqClasses ConEQ(*LiveInts); 1344 unsigned NumComp = ConEQ.Classify(&LI); 1345 if (NumComp > 1) { 1346 report("Multiple connected components in live interval", MF); 1347 *OS << NumComp << " components in " << LI << '\n'; 1348 for (unsigned comp = 0; comp != NumComp; ++comp) { 1349 *OS << comp << ": valnos"; 1350 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), 1351 E = LI.vni_end(); I!=E; ++I) 1352 if (comp == ConEQ.getEqClass(*I)) 1353 *OS << ' ' << (*I)->id; 1354 *OS << '\n'; 1355 } 1356 } 1357 } 1358 } 1359 } 1360 1361
