| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 74 MVT ArgVT = Ins[i].VT;
92 MVT VT = Outs[i].VT;
94 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
106 MVT VT = Outs[i].VT;
108 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
111 << EVT(VT).getEVTString()
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 84 EVT ArgVT = Ins[i].VT;
120 EVT VT = Outs[i].VT;
122 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this, -1, -1, false)){
124 << VT.getEVTString() << "\n";
150 EVT ArgVT = Outs[i].VT;
188 EVT VT = Ins[i].VT;
190 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this, -1, -1, false))
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXSelectionDAGInfo.cpp | 54 EVT VT = MVT::i32;
69 Loads[i] = DAG.getLoad(VT, dl, Chain,
101 VT = MVT::i16;
104 VT = MVT::i8;
108 Loads[i] = DAG.getLoad(VT, dl, Chain,
124 VT = MVT::i16;
127 VT = MVT::i8;
|
| PTXISelDAGToDAG.cpp | 113 EVT VT = Node->getValueType(0);
114 assert(VT.isSimple() && "READ_PARAM only implemented for MVT types");
116 MVT Type = VT.getSimpleVT();
138 return CurDAG->getMachineNode(OpCode, dl, VT, Ops, 4);
151 EVT VT = Value->getValueType(0);
152 assert(VT.isSimple() && "WRITE_PARAM only implemented for MVT types");
154 MVT Type = VT.getSimpleVT();
|
| /external/llvm/utils/TableGen/ |
| CallingConvEmitter.cpp | 72 Record *VT = VTs->getElementAsRecord(i);
74 O << "LocVT == " << getEnumName(getValueType(VT));
|
| DAGISelMatcher.cpp | 210 OS.indent(indent) << "EmitInteger " << Val << " VT=" << VT << '\n';
215 OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << VT << '\n';
224 OS << " VT=" << VT << '\n';
293 return HashString(Val) ^ VT;
|
| CodeGenTarget.cpp | 432 MVT::SimpleValueType VT;
437 VT = OverloadedVTs[MatchTy];
443 VT == MVT::iAny || VT == MVT::vAny) &&
446 VT = getValueType(TyEl->getValueAsDef("VT"));
448 if (EVT(VT).isOverloaded()) {
449 OverloadedVTs.push_back(VT);
454 if (VT == MVT::isVoid)
457 IS.RetVTs.push_back(VT);
[all...] |
| IntrinsicEmitter.cpp | 177 static void EmitTypeForValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
178 if (EVT(VT).isInteger()) {
179 unsigned BitWidth = EVT(VT).getSizeInBits();
181 } else if (VT == MVT::Other) {
184 } else if (VT == MVT::f16) {
186 } else if (VT == MVT::f32) {
188 } else if (VT == MVT::f64) {
190 } else if (VT == MVT::f80) {
192 } else if (VT == MVT::f128) {
194 } else if (VT == MVT::ppcf128)
[all...] |
| /external/clang/include/clang/AST/ |
| DeclContextInternals.h | 155 DeclsTy *VT = new DeclsTy();
156 VT->push_back(OldD);
157 Data = VT;
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
66 Loads[i] = DAG.getLoad(VT, dl, Chain,
98 VT = MVT::i16;
101 VT = MVT::i8;
105 Loads[i] = DAG.getLoad(VT, dl, Chain,
121 VT = MVT::i16;
124 VT = MVT::i8;
|
| /external/llvm/lib/VMCore/ |
| ValueTypes.cpp | 29 EVT VT;
30 VT.LLVMTy = IntegerType::get(Context, BitWidth);
31 assert(VT.isExtended() && "Type is not extended!");
32 return VT;
35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT,
38 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 85 EVT VT = Node->getValueType(ResNo);
88 if (TLI->isTypeLegal(VT))
89 UseRC = TLI->getRegClassFor(VT);
110 EVT VT = Node->getValueType(Op.getResNo());
111 if (VT == MVT::Other || VT == MVT::Glue)
138 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
144 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
147 DstRC = TLI->getRegClassFor(VT);
403 EVT VT, DebugLoc DL)
[all...] |
| SelectionDAGPrinter.cpp | 94 EVT VT = Op.getValueType();
95 if (VT == MVT::Glue)
97 else if (VT == MVT::Other)
|
| FunctionLoweringInfo.cpp | 173 EVT VT = ValueVTs[vti];
174 unsigned NumRegisters = TLI.getNumRegisters(Fn->getContext(), VT);
211 unsigned FunctionLoweringInfo::CreateReg(EVT VT) {
212 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
273 "PHIs with non-vector integer types should have a single VT.");
|
| ResourcePriorityQueue.cpp | 97 EVT VT = ScegN->getValueType(i);
98 if (TLI->isTypeLegal(VT)
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
135 EVT VT = Op.getNode()->getValueType(Op.getResNo());
136 if (TLI->isTypeLegal(VT)
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
335 EVT VT = SU->getNode()->getValueType(i);
336 if (TLI->isTypeLegal(VT)
337 && TLI->getRegClassFor(VT)
338 && TLI->getRegClassFor(VT)->getID() == RCId
[all...] |
| LegalizeTypesGeneric.cpp | 374 EVT VT = N->getValueType(0);
375 assert(VT.getVectorElementType() == N->getOperand(0).getValueType() &&
377 unsigned NumElts = VT.getVectorNumElements();
383 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
|
| LegalizeVectorOps.cpp | 277 EVT VT = Op.getValueType();
280 EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
293 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
390 EVT VT = Op.getOperand(0).getValueType();
401 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
402 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
403 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand)
406 assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits()
411 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
412 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2)
[all...] |
| ScheduleDAGFast.cpp | 218 EVT VT = N->getValueType(i);
219 if (VT == MVT::Glue)
221 else if (VT == MVT::Other)
226 EVT VT = Op.getNode()->getValueType(Op.getResNo());
227 if (VT == MVT::Glue)
569 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
571 TRI->getMinimalPhysRegClass(Reg, VT);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 211 EVT VT = Node->getValueType(0);
212 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
|
| /external/clang/lib/CodeGen/ |
| CodeGenTypes.cpp | 443 const VectorType *VT = cast<VectorType>(Ty);
444 ResultType = llvm::VectorType::get(ConvertType(VT->getElementType()),
445 VT->getNumElements());
|
| /external/guava/guava/src/com/google/common/base/ |
| Ascii.java | 167 public static final byte VT = 11;
|
| /external/llvm/include/llvm/Target/ |
| TargetCallingConv.h | 113 MVT VT;
116 InputArg() : VT(MVT::Other), Used(false) {}
117 InputArg(ArgFlagsTy flags, EVT vt, bool used)
119 VT = vt.getSimpleVT();
129 MVT VT;
135 OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed)
137 VT = vt.getSimpleVT();
|
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 240 EVT VT = (strcmp(Modifier+6,"64") == 0) ?
243 Reg = getX86SubSuperRegister(Reg, VT);
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 261 EVT VT = LS->getMemoryVT();
263 if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
264 assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
266 if (VT == MVT::f32)
408 EVT VT = LHS.getValueType();
409 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
410 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
413 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 222 EVT VT) const {
228 if (VT == MVT::i8)
235 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
590 EVT VT = Op.getValueType();
599 VT, N->getOperand(0), N->getOperand(1));
602 VT, N->getOperand(0), N->getOperand(1));
605 VT, N->getOperand(0), N->getOperand(1));
618 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
624 dl, VT, Victim);
813 EVT VT = Op.getValueType()
[all...] |
